1. skrec ICRRE 2015
Session - 1; Track - 5

2. selective harmonic elimination for a new symmetric multilevel inverter
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selective harmonic elimination for a new symmetric multilevel inverter
Ms. T.Preethika.,B.E.,(M.E-PED) PG Student Department of EEE
Mrs. S.Menaka.,M.E.,(Ph.D) Asst. Prof Department of EEE

3. overview Objective Introduction Existing Topology Proposed Topology
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overview
Objective
Introduction
Existing Topology
Proposed Topology
Harmonic Reduction
Selective Harmonic Elimination Method
Simulation and Results
Conclusion

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objective
To design a new topology with reduced number of switching devices.
To apply Selective Harmonic Elimination for the designed topology and reduce the harmonic content of it.

5. Introduction Inverter are basically have 3 level.
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Introduction
Inverter are basically have 3 level.
Several inverter circuits are combined to form the MLI.
Gives increased level of Output Voltage.
No. of level increases pure sine wave is obtained.
Applied in the areas of UPS, Induction Heating, HVDC Power Transmission and Variable frequency Drives.

6. Cascaded Multilevel Inverter
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Existing topology
Cascaded Multilevel Inverter
Referred MLI Topology

7. switching signals State No. Switching States Voltage Level 1 S1, S2
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switching signals
State No.
Switching States
Voltage Level 1
S1, S2
+2Vdc 2
S1, S5
+Vdc 3
S5, S6 4
S3, S6
-Vdc 5
S3, S4
-2Vdc

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proposed topology
The new topology is designed by eliminating one switch with its diode package.
The switches are remodeled and the switching sequence is rearranged.
Such that the new topology can produce high number of output level with very much reduced number of switches.
The newly designed topology is applicable for only symmetric mode of operation.

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generalized circuit
EXISTING SYSTEM
PROPOSED SYSTEM

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switching states

11. parameters For N - level Number of DC Voltage Sources is given by
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parameters
For N - level
Number of DC Voltage Sources is given by
Number of Switches is given by

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7 LEVEL topology

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switching pulses

14. voltage equation Voltage Equation for 7 level
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voltage equation
Voltage Equation for 7 level
Voltage Equation for n level

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harmonic reduction
The harmonics are reduced using modulation techniques.
The modulation is method where the signal is varied or corrected according to the additional signal parameters
The modulated signals are given to the device to get proper output.

16. selective harmonic elimination pulse width modulation
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selective harmonic elimination pulse width modulation
In this method, harmonics are eliminated according to the degree of the inverter which is given by
where M - level of inverter.
The degree of the inverter represents the number of switching angles
For a desired peak output voltages, the switching angles should be obtained such that
0<δ1<δ2<δ3<π/2

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Contd..
Among the 'd' degrees, one is used for controlling the voltage magnitude and others for eliminating harmonics.

18. contd.. For 7 level SCMLI, the degree of the inverter is 3.
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contd..
For 7 level SCMLI, the degree of the inverter is 3.
So that we can eliminate the 3rd and 5th harmonic element by solving the following equation using Newton Raphson Jacobian Matrix Method

19. nrjm algorithm Assuming random values for switching angles
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nrjm algorithm
Assuming random values for switching angles
Initializing mi = 0
Solving the matrix F(δ), B(mi) and J(δ)
Comupute Δδ during iteration.

20. δ(k+1)=cos-1(abs(cos(δ(k+1))))
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Contd...
Switching angles are updated
δ(k+1) = δ(k)+Δδ(k)
Fesible switching angles are obtained
δ(k+1)=cos-1(abs(cos(δ(k+1))))
Steps (3) to (6) is repeated to attain error goal
Value of mi is incremented
Steps (2) to (8) is repeated for the whole mi

21. simulation for 7 level MLI
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simulation for 7 level MLI
Number of SDCS Sources : 3
SDCS Voltage : 100V
Resistance : 100Ω
Inductance : 1.25μH
Output Voltage : 300V
THD : 24.31%

22. simulink model for 7 level
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simulink model for 7 level

23. switching pulse generator
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switching pulse generator

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output & THD

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she modulated pulses

26. SHE modulated output & THD
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SHE modulated output & THD

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3 phase SMLI

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3 phase output & THD

29. Number of switch is reduced in the basic block .
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conclusion
Number of switch is reduced in the basic block .
The 5 level output is obtained using only 5 switches.
No need of adding another block to increase two levels in output.
Instead of adding another block with 6 switches, only one switch with its diode package and a dc source can be connected in series within the basic block.

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switching comparison

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reference
[1]Ataollah Mokhberdoran and Ali Ajami, "Symmetric and Asymmetric Design and Implementation of New Cascaded multilevel Inverter Topology", IEEE Transactions on Power Electronics, DOI /TPEL
[2]A. Nami, F. Zare, A. Ghosh, and F. Blaabjerg, “A hybrid cascade converter topology with series - connected symmetrical and asymmetrical diode-clamped H-bridge cells,” IEEE Trans. Power Electron., vol. 26, no. 1, pp , Jan
[3]E. Babaei, “A cascade multilevel converter topology with reduced number of switches” IEEE Trans. Power Electron., vol. 23, no. 6, pp , Nov
[4]Farhadi Kangarlu, Ebrahim Babaei, “A Generalized Cascaded Multilevel Inverter Using Series Connection of Sub-multilevel Inverters” IEEE Trans, Power Electron, Vol. 28, No. 2, pp , Feb 2013.

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contd.
[5]Ebrahim Babaei, Somayeh Alilu, and Sara Laali, "A New General Topology for Cascaded Multilevel Inverters With Reduced Number of Components Based on Developed H-Bridge", IEEE Trans. Industrial Electronics, vol. 61, no. 8, pp , Aug 2014.
[6]José Rodríguez, Jih-Sheng Lai, Fang Zheng Peng "Multilevel Inverters: A Survey of Topologies, Controls, and Applications" IEEE Trans. Industrial Electronics, Vol. 49, no. 4, pp AUGUST 2002.
[7]Jagdish Kumar, Biswarup Das and Pramod Agarwal, “Selective Harmonic Elimination Technique for a Multilevel Inverter ”, Fifteenth National Power Systems Conference, IIT Bombay, pp , Dec 2008.

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thank you