1. Engr. Noshina Shamir UET, Taxila
VLSI Design Lecture1
Engr. Noshina Shamir
UET, Taxila

2. Outline A Brief History CMOS Gate Design Pass Transistors
CMOS Latches & Flip-Flops
Standard Cell Layouts
Stick Diagrams
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3. A Brief History 1958: First integrated circuit
Flip-flop using two transistors
Built by Jack Kilby at Texas Instruments
2008
Intel Pentium 4 mprocessor (55 million transistors)
512 Mbit DRAM (> 0.5 billion transistors)
53% compound annual growth rate over 45 years
No other technology has grown so fast so long
Driven by miniaturization of transistors
Smaller is cheaper, faster, lower in power!
Revolutionary effects on society
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4. Annual Sales 1018 transistors manufactured in 2003
100 million for every human on the planet
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5. Invention of the Transistor
During the first half of the twentieth century, electronic circuits used large, expensive, power-hungry, and unreliable vacuum tubes.
In 1947, John Bardeen and Walter Brattain built the first functioning transistor at Bell Laboratories, shown in Figure
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6. It was nearly classified as a military secret, but Bell Labs publicly introduced the device the following year.
”We have called it the Transistor, T-R-A-N-S-I-S-T-O-R, because it is a resistor or semiconductor device which can amplify electrical signals as they are transferred through it from input to output terminals. It is, if you will, the electrical equivalent of a vacuum tube amplifier. But there the similarity ceases. It has no vacuum, no filament, no glass tube. It is composed entirely of cold, solid substances.”
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7. Ten years later, Jack Kilby at Texas Instruments realized the potential for miniaturization if multiple transistors could be built on one piece of silicon.
His first prototype of an integrated circuit, constructed from a germanium slice and gold wires.
The invention of the transistor earned the Nobel Prize in Physics in 1956 for Bardeen, Brattain, and their supervisor William Shockley.
Kilby received the Nobel Prize in Physics in 2000 for the invention of the integrated circuit.
By the 1960s, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) began to enter production.
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8. In 1963, Frank Wanlass at Fairchild described the first logic gates using MOSFETs.
Fairchild’s gates used both nMOS and pMOS transistors, earning the name Complementary Metal Oxide Semiconductor, or CMOS.
The circuits used transistors but consumed only nano watts of power, six orders of magnitude less than their bipolar counterparts.
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9. Moore’s Law 1965: Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale
Transistor counts have doubled every 18 months
Integration Levels
SSI: 10 gates
MSI: gates
LSI: 10,000 gates
VLSI: > 10k gates
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10. Transistor Types Bipolar transistors npn or pnp silicon structure
Small current into very thin base layer controls large currents between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between source and drain
Low power allows very high integration
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11. Silicon Lattice Transistors are built on a silicon substrate
Silicon is a Group IV material
Forms crystal lattice with bonds to four neighbors

12. Dopants Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type)
Group III: missing electron, called hole (p-type)

13. MOSFET
A Metal-Oxide-Semiconductor (MOS) structure is created by superimposing several layers of conducting and insulating materials to form a sandwich-like structure.
These structures are manufactured using a series of chemical processing steps involving:
Oxidation of the silicon
selective introduction of dopants
etching of metal wires and contacts.

14. Power Supply Voltage GND = 0 V In 1980’s, VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

15. Transistors as Switches
We can view MOS transistors as electrically controlled switches
Voltage at gate controls path from source to drain

16. Transistors as Switches
We can view MOS transistors as electrically controlled switches
Voltage at gate controls path from source to drain

17. Series and Parallel nMOS: 1 = ON pMOS: 0 = ON Series: both must be ON
Parallel: either can be ON
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18. CMOS Inverter A Y 1

19. Complementary CMOS Complementary CMOS logic gates
nMOS pull-down network
pMOS pull-up network
a.k.a. static CMOS
Pull-up OFF
Pull-up ON
Pull-down OFF
Z (float) 1
Pull-down ON
X (crowbar)
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20. Conduction Complement
Complementary CMOS gates always produce 0 or 1
Ex: NAND gate
Series nMOS: Y=0 when both inputs are 1
Thus Y=1 when either input is 0
Requires parallel pMOS
Rule of Conduction Complements
Pull-up network is complement of pull-down
Parallel -> series, series -> parallel
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21. CMOS Inverter A Y 1

22. CMOS Inverter A Y 1

23. Verilog Code for NOT Gate
// Not gate Switch Level Code
module notgate(y,x);
output y;
input x;
supply1 pwr;
supply0 gnd;
pmos(y,pwr,x);
nmos(y,gnd,x);
endmodule
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24. Verilog code nmos n1(out, data, control); // instantiate a nmos switch
pmos p1(out, data, control); // instantiate a pmos switch
A CMOS switch is instantiated as shown in below,
cmos cl(out, data, ncontrol, pcontrol);//instantiate cmos gate or
cmos (out, data, ncontrol, pcontrol); //no instance name given
supply1 vdd ;
supply0 gnd ;
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25. // Not Gate Stimulus module test_notgate; wire y; reg x;
notgate test(y,x);
initial
begin
x=1'b0;
#10 x=1'b1;
end
endmodule
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26. CMOS NAND Gate A B Y 1

27. CMOS NAND Gate A B Y 1

28. CMOS NAND Gate A B Y 1

29. CMOS NAND Gate A B Y 1

30. CMOS NAND Gate A B Y 1

31. Nand gate Switch Level Code
module nandgate(out,x,y);
output out;
input x,y;
wire c;
supply1 pwr;
supply0 gnd;
pmos(out,pwr,x);
pmos(out,pwr,y);
nmos(c,gnd,x);
nmos(out,c,y);
endmodule
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32. Nand Gate Stimulus module test_nandgate; wire out; reg x,y;
nandgate test(out,x,y);
initial
begin
x=1'b0;y=1'b0;
#10 x=1'b0;y=1'b1;
#10 x=1'b1;y=1'b0;
#10 x=1'b1;y=1'b1;
end
endmodule
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33. CMOS NOR Gate A B Y 1

34. Nor gate Switch Level Code
module norgate(out,x,y);
output out;
input x,y;
wire c;
supply1 pwr;
supply0 gnd;
pmos(c,pwr,x);
pmos(out,c,y);
nmos(out,gnd,x);
nmos(out,gnd,y);
endmodule
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35. Nor Gate Stimulus module test_norgate; wire out; reg x,y;
norgate test(out,x,y);
initial
begin
x=1'b0;y=1'b0;
#10 x=1'b0;y=1'b1;
#10 x=1'b1;y=1'b0;
#10 x=1'b1;y=1'b1;
end
endmodule
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36. 3-input NAND Gate Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0

37. 3-input NAND Gate Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0

38. CMOS Gate Design Activity: Sketch a 4-input CMOS NAND gate
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39. CMOS Gate Design Activity: Sketch a 4-input CMOS NOR gate
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40. Compound Gates Compound gates can do any inverting function Ex:
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41. Example: O3AI
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42. Example: O3AI
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43. Signal Strength Strength of signal
How close it approximates ideal voltage source
VDD and GND rails are strongest 1 and 0
nMOS pass strong 0
But degraded or weak 1
pMOS pass strong 1
But degraded or weak 0
Thus nMOS are best for pull-down network
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44. Pass Transistors Transistors can be used as switches
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45. Pass Transistors Transistors can be used as switches
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46. Transmission Gates Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well
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47. Transmission Gates Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well
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