1. Digital Down Converter (DDC)
High speed multi-antenna radio receiver for applications in radar and communications
Weiwei Sun, John Sahr
University of Washington
We present an initial results from ROACH2-based radio receiver used for ionospheric physics, radar and communications. The system is composed of a ROACH2 board with two ADC5G cards which can directly sample the signals up to 5GSPS. This system permits unaliased Nyquist sampling well into the UHF spectrum, while providing simultaneous access to VHF and UHF illuminators without duplication of the RF signal path.
The receiver is able to extract multiple frequency channels from the VHF and UHF spectrum on the same antenna and can produce over 100dB processing gain which provide better sensitivity for week scatterers for radar applications or week channels for communications. The FPGA design also allow the receiver to select and change any mixer frequency and output bandwidth at run time, without redesigning FPGA.
The results of two typical FGPA designs in duel 2.5GHz and single 5GHz modes B D l1 l2
ground plane A C
Antenna array orientation
Antenna: 15 cm long monopole
Ground plane: 61 x 61 cm2
l1 = 31.5cm
l2 = 18.5cm
Ant A
Ant C
Ant D
Ant B
zoom-in
Channel 1
mixer f1=98MHz
bw = 31.25MHz
zoom-in
Channel 2
mixer f2=575MHz
bw = 31.25MHz
The figure on the right shows the spectrum of the data taken in the 2.5GHz mode (4 RF inputs(4 antennas), sampler rate at 2.5GHz) with 2 channels (mixer frequencies at 96MHz and 575MHz, output bandwidth of around 30MHz for both channels) per antenna. The top shows the channel of entire FM spectrum for 4 antennas and the bottom shows an KONG Digital TV station at 575MHz and an adjacent station at 587MHz.
Diagram of the processing flow
2.5GHz ADC
Digital Down Converter (DDC)
…,x9,x8,..,x1,x0
…, x8, x0
…, x9, x1
…, x10, x2
…, x15, x7
…, x11, x3
…, x12, x4
…, x13, x5
…, x14, x6
…, zi8, zi0
…, zi9, zi1
…, zi10, zi2
…, zi15, zi7
…, zq11, zq3
…, zq12, zq4
…, zi13, zi5
…, zi14, zi6
Polyphase Filter
(48 coefficients with precision 16 bits
downsampling by 8)
…,di2,di1,di0
8 bits,
2.5GHz
8 bits, 2.5GHz
with each stream at 312.5MHz
16 bits, 2.5GHz
16 bits,
312.5MHz baseband
CIC Filter (downsampling by n)
(large decimation ratio,
less computation complexity)
…,si2,si1,si0
312.5/n MHz
10GbE Buffer
DDS generator
8 DDS Xilinx compilers
frequency resolution: 100MHz
8 parallel streams of sine signal at 2.5GHz,
and 8 parallel streams of cosine signal at 2.5GHz.
Each stream at 312.5MHz
…,ys0,
…,ys1,
…,ys2,
…,ys3,
…,..,
…,ys7
Polyphase LP Filter
(same as above)
CIC Filter
…, zq9, zq1
…, zq10, zq2
…, zi11, zi3
…, zi12, zi4
…, zq8, zq0
…, zq13, zq5
…, zq14, zq6
…, zq15, zq7
…,dq2,dq1,dq0
…,sq2,sq1,sq0
…,yc0,
…,yc1,
…,yc2,
…,ycs3,
…,yc7
I channel
Q channel
Ant A
Ant B
The figure on the right shows the spectrum of the data taken in the 5GHz mode (2 RF inputs(2 antennas), sampler rate at 5GHz) with one channel (mixer frequencies at 1955MHz, output bandwidth of about 55MHz) per antenna.
It indicates a direct sampling at 2GHz without aliasing.
Cellular band
ROACH2 board specification
Xilinx Virtex6 FPGA
XC6VSX475T
(312.5MHz)
Z-DOK+
8 bits, 1.25Gsps
RF In A
RF In C
(a) Dual 2.5GSPS mode
ADC5G
dual 2.5 GSPS
Out A0
Out A1
Out C0
Out C1
Xilinx Virtex6 FPGA
XC6VSX475T
(312.5MHz)
Z-DOK+
8 bits, 1.25Gsps
RF In A
(a) Single 5GSPS mode
ADC5G
single 5 GSPS
Out A0
Out A1
Out C0
Out C1
f0-55/2MHz
f0=1955MHz
f0+55/2MHz
Bandwidth=55MHz
Spectrum centered at 1955MHz with bandwidth of 55MHz
FPGA resource usage for 2.5GHz mode with 1/2 channels
 FPGA Virtex 6
Total number
1-channel design
2-channel Design
DSP48E1
2016
512 (25%)
1152 (57%) 
Slice Registers
(mainly used as FF)
595,200
51,343 (8%)
149,360 (25%)
Slice LUTs
(mainly used as logic and memory)
297,600
16,819 (5%)
70,375 (23%)
Spectrum representation of the processing flow
The receiver consists of 2 ADC5G cards and a Xilinx Virtex 6 FPGA. Each ADC is clocked at 2.5GHz, and can sample at 2.5GHz (two RF inputs) or 5GHz (single input). Xilinx clocks at 312.5MHz, 1/8th of the ADC clock.
1250
MHz
-1250
frequency f0
-f0
-f1 f1
Power (dB)
Stage 0: Wideband real-valued raw data
ROACH2
Amplifier
(Optional)
Analog LP Filter
0-1250MHz
10GbE link
GPU/PC
2.5GHz (5Gsps) ADC5G
Digital I/Q mixer
(or DDS)
Polyphase LP Filter
Cascaded-Integrator-Comb (CIC) Filter
10GbE buffer
GPS Monopole Antenna
Processing flow in FPGA
Receiver architecture
The RF signal is collected by a short monopole antenna, and directly sampled by the fast digitizer after a low pass filter. The signal processing is performed digitally in the FPGA. A digital I/Q mixer is adopted which digitally translates the desired spectrum to base band in I/Q form, followed by a polyphase FIR filter and a cascaded-integrator comb (CIC) filter reduces the bandwidth and data rate. Finally the data is sent off the FPGA through the 10Gb Ethernet port.
The figure above shows the processing chain for one antenna and one selected RF channel.  In practice this is duplicated for each antenna and RF channel combination. The ROACH2/Virtex 6 can handle up to 16 RF/Channel down conversions simultaneously, that is, 4 antennas, each with 4 channels.
Slices registers for 2-channel design are more than twice than the 1-channel design. As the design gets complex and more FPGA resources are used, the time-enclosure becomes harder with the 312.5MHz rate which is approaching the FPGA maximum clock rate. Timing is solved by adding delays which uses additional slice registers.
The DSP48E1 blocks are mainly used by the polyphase filter. In 2-channel design, the number doubles and is also half of the total number of DSP blocks. We will expect 4-channel design would be very difficult to fit in the FPGA. Some compromise will be made, such as shorten the length of filter coefficients or bit width.
1250MHz
-1250 MHz
frequency
-2f0
-f1-f0
f1-f0
Power (dB)
Stage 1: After digital down conversion
1250/8
Comparison with traditional analog receivers and Software-Defined Radio
ADC speed
Design flexibility
Analog Receivers / SDR
Low (USDR 200MHz)
Fixed configuration due to the analog components
Our software receiver
High (2.5GHz/5GHz)
Different configurations due to the programmable FPGA
156.25MHz
MHz
frequency
Power (dB)
Stage 2: After polyphase filter
(LP filtering and downsampling by 8)
156.25/n
MHz /n
frequency
Power (dB)
Stage 3: After CIC filter
(LP filtering and downsampling by n)
High speed digitizer provides unaliased access to high frequency such as GPG signals (1.5GHz), and releases the requirement for anti-aliase analog filters. More important, the downconversion and downsampling will produce much larger processing gains, which provides better sensitivity for weak target detection for radar application and low-power channel measurement for communication.
The programmable FPGA indicates the receiver can be configured with different processing chains, which tremendously increase the flexibility and usefulness of the receiver.

2. Wideband real-valued raw data
1250MHz
-1250MHz
frequency f0
-f0
-f1 f1
Power (dB)
Wideband real-valued raw data