1. Final Project Report 64 points FFT
Adviser: Prof. An-Wei Wu
Mentor: 陳圓覺
Reporter: 洪聖揚

2. Outline The design of 64 points FFT RTL code
The synthesis of FFT RTL code
Area improving
Problem encountered
Future Work
Conclusion

3. The structure of FFT RTL code
Goal :reduce timing, area, and power
butterfly
1.Two stages
2. BFI, BFII
Combinational ckt
multipliers
Top module
FFT
1.Parameterized twiddle factors
2.Folded twiddle factors
3. Multiplier I , Multiplier II
Sequential ckt
registers
1.Gate blocking
2.Non-shifted registers
counter

4. Bits Design in FFT

5. The Design of Butterfly

6. The Design of Multiplier
Parameterized twiddle factors
--fixed twiddle factor bit in circuit
Folded twiddle factors
-- use 9 twiddle factors in Multiplier1, 3 twiddle factors in Multiplier2

7. Figures of Multiplier Design
9 sets of twiddle factors
input
Two type control signals
twiddle
Twiddle factor = 1+j0?
Twiddle factors
‧‧‧‧‧‧‧
‧‧‧‧‧‧‧ No
Twiddle factor
Yes
Ｍｕｘ
‧‧‧‧‧‧‧
output
‧‧‧‧‧‧‧
multiplier

8. The design of Register Gate blocking skills --for reduce power
non-shifted registers
-- use counter to address registers

9. Figure of Registers Design1
‧‧‧ 2 ３２
Register 2
‧‧‧ １ ２ １６
Data to save
Register 3
‧‧‧ １ ２ ８
Register 4 １
‧‧‧ ２ ４
Register 5 １
‧‧‧ ２
Register 6 １
Control signal

10. Verification

11. Result of RTL Level Test 10 sets and calculation SQNR
Lowest SQNR of test sets: 50.3dB
The best three sets :
51.97, 52.92, dB

12. Reducing non-useful registers
The Tuning of Area
Improve coding style
*Tuning bits of output and internal data
Reducing non-useful registers

13. Result After Synthesis
Input bits=11 , Twiddle bits=11, Output bit=17
Area
Timing
Power
Score
19.73ns uW
21.61ns uW

14. Problem Encountered in Design
Folded data design
Address registers

15. Problem Encountered in Synthesis
Parameter & illegal design
Unfamiliar with synthesis environment
Gate level simulation

16. Future Work Tuning data for reducing area Improve Multipliers
Improve clock period

17. Conclusion Pipeline structure is very useful in debug and design
Gate blocking design is low power but much effort for best design
Hardware language is not only the task of function work.