1. ETD PID meeting We had many presentations dedicated to the PM test .
First studies of H8500 with Bari scanning setup
A study of afterpulse effect due to Helium permeation in the H8500 MaPMT
Studies of cross-talk in the HM8500
Use the dy12 pin to inject a charge signal on each pixel anode
Developments for FTOF :
Design of a 16-channel board based on SAMLONG chips (3.2GHz-1k analog memory)
Design of a 64-channel system based on four 16-channel boards synchronized by a controller board
320-channel system is also under design
On behalf of PID group
Christophe Beigbeder
Dec 13th 2011

2. 25 power supplies (5 global, 20 local)
1.6mm thick
10 layers
233 x 220 mm²
3200 components
25 power supplies (5 global, 20 local)
4-channel blocks used as mezzanine
Front-end block has been integrated in a mezzanine. Permits hardware debug and predesign of firmware for the 16-channel board (should be sold by CAEN soon).
Preliminary resuts:
Time jitter < 10ps rms per channel even between different mezzanines
Christophe Beigbeder
Dec 13th 2011

3. Present and future board features (not exhaustive)
Possibility to add an individual DC offset on each signal
Possibility to chain channels by groups of 2
2 individual trigger discriminators on each channel
External and internal trigger + numerous modes of triggering on coïncidence (11 possibilities including two pulses on the same channel => useful for afterpulse studies
Embedded digital CFD for time measurement
Embedded signal amplitude extraction
Embedded charge mode (integration starts on threshold or at a fixed location) => high rates (~ 3.5 kEvents/s)
2 extra memory channels for digital signals
One pulse generator on each input
External clock input for multi-board applications
Embedded USB and Serial Lite/Fibre Channel/Conet interfaces
Possibility to program the FPGAs via USB/Backplane/Altera Blaster
Christophe Beigbeder
Dec 13th 2011

4. Electronics for Barrel
We submitted the TDC SCATS beginning of November
We start to design the test board for the SCATS which will be submitted in January
In parallel we are designing the module to equip the Slac
We have a draft of the TDR
The aim of the meeting was to agree on a base line design
To be able to answer to the two requests concerning the integration and power supplies.
According to our TDR we will be able to review manpower and costing.
Christophe Beigbeder
Dec 13th 2011

5. Context and requirements
Radiation environment
Architecture description
TDC part
Christophe Beigbeder
Dec 13th 2011

6. The backplane for ECS and FCTS signals
The Front end crate
TDC description
and synopsis
The backplane for ECS and FCTS signals
The motherboard is fixed on the FBLOCK, handle the Pm and receive the FE board
Christophe Beigbeder
Dec 13th 2011

7. View of the FE boards on the FBLOCK with the Fan tray module
Front end board description
The crate
# option to be developed
Front end board synopsis
Power-Cooling
Christophe Beigbeder
Dec 13th 2011

8. Questionnaire Dec 13th 2011 Christophe Beigbeder
SuperB integration questionnaire
Data: xx\xx\xx
Sub detector name: FDIRC
Author:
Electronics:
Number of electronic channel: 18,432
Number of tubes: 48 x 12 = 576
Power dissipated per tube: ~15W
Volume occupied by the electronics (drawings of electronic modules):
Boards are plugged on the Fblock thanks to a mechanical structure. This structure FB_crate looks like a crate with guides for inserting boards. It also fastens fans for cooling and a power supply. The size of the crate has the size of the Fblock + the size of the power supply and the fans underneath. The depth is around 40 cm.
Christophe Beigbeder
Dec 13th 2011

9. Frequency access on the detector per year: 2-3 / year
Max tolerable distances between the detectors to the electronic modules:
Access frequency on the external electronic per year: no special need .Global policy ?
Frequency access on the detector per year: 2-3 / year
Modularity of the electronic unit (housing racks): 12 FB_Crates.
Number and size of power cable: 12 copper cables . ~ 2 cm (380 V)
HV cables ? 8/mother board * 12 sectors
Number and size of Read-out cables or fibers: 12 optical fibers.~ 1cm
Number and size of slow control cables: 12 ECS cat5 copper cables. ~ 1cm
12 maraton cables ~ 2 cm
Can-bus for HV slow control : Yes
Minimum bending radius. ?
Shielding requirements (thermal and electrical) : magnetic and electrical shielding.
Information drawings on the cable distribution on the detector geometry: ?
Cooling system. Water and air
Requirement of cooling system: 500W/sector
Power, flow, temperature and type of fluid: 6kW total, C, 300m3/hour/ crate
Allowed detector temperature variations: constant
Size of the chiller: on the top of the detector ?
Cooling pipes distribution at sub detector ends (drawings): ?
Describe other requirements that have an impact of the space available like auxiliary equipment, minimum space for accessibility, etc Power supplies imbedded inside magnetic shield. May share with CDC & ??
Describe other requirements that have an impact of the space available like space for the commissioning operations and assembly. ?
Christophe Beigbeder
Dec 13th 2011

10. Dec 13th 2011 Christophe Beigbeder 3,3 V 5V -5V One ~ 2-3 mV 8 * 12
DC/DC power Supply V1 V2 V3 V4 V5
Comment, if any
Required Voltage level (V)
 3,3 V
 5V
 -5V
Total power (W)
 6 KW
Number of input connections/cables
 12
Current absorption per input cable
 500 W
Number of output connections/cables
 One
Current absorption per ouput cable  ?
Purpose (pre-regulation followed by linear regulator, final value, etc.)
Power supply location (detector area, outside detecotr area)
 12 power supplies inside the shield
Maximum ripple (mV), or
 ~ 2-3 mV
Maximum ripple (%)
HV for detectors bias
 ~ 1KV
 15 W
 8 * 12
 close to the detector but in a safe area
pp noise (mV), or
pp noise (%)
Christophe Beigbeder
Dec 13th 2011