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Some Historical Context And Some Prognostication
SystemC Some Historical Context And Some Prognostication Copyright 2013 Forte Design Systems Copyright Forte Design Systems 2012
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Agenda Tell Them What You’re Going To Tell Them
“SystemC has been developed with a bunch of different motivations. Some of these have taken off, others not-so-much. The future of SystemC is merging some of the use models together and delivering on some of the original motivations” Copyright 2013 Forte Design Systems
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Early 90’s Lots of Groups Working On System Design
“Y diagram” System Design Vision: Top-down System Synthesis HW/SW System Implementation Functional Elements Prior to HW/SW Partitioning Platform Elements Berkeley POLIS/Ptolemy Synopsys System Modeling Group Cadence VCC Univ Nantes NCSE CoWare N2C Irvine SpecC Copyright 2013 Forte Design Systems
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Late 90’s Next Generation Of HLS Emerging
Celoxica HandelC CynApps Cynlib C-based High-level Synthesis Vision Synopsys C Synthesis Group Adding HW structure & concurrency to C Extending C language Adding C++ Classes Focus was synthesizing from description including HW structure & high-level behavior Irvine SpecC Cadence VCC Synopsys System Modeling Group CoWare N2C Berkeley POLIS/Ptolemy Univ Nantes NCSE Irvine SpecC Cadence VCC Synopsys System Modeling Group CoWare N2C Berkeley POLIS/Ptolemy Univ Nantes NCSE Copyright 2013 Forte Design Systems
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The Origins of SystemC Synopsys created Open SystemC Initiative
Celoxica HandelC Synopsys created Open SystemC Initiative Intended for synthesis and system modeling Initial implementation only included low-level features needed for synthesis CynApps Cynlib Synopsys C Synthesis Group SystemC V0.9 Sep ‘99 Synopsys “Scenic” Berkeley POLIS/Ptolemy Synopsys System Modeling Group Cadence VCC Univ Nantes NCSE CoWare N2C Irvine SpecC Copyright 2013 Forte Design Systems
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SystemC Motivations Y-diagram top-down system design
From Synopsys System Modeling Group Y-diagram top-down system design System architecture modeling High-level synthesis From Synopsys C Synthesis Group Copyright 2013 Forte Design Systems
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1999 - Open SystemC Initiative
A Synopsys initiative Criticized as not open enough License Governance Key industry players on the outside OSCI Synopsys CoWare Support from numerous system/semi companies CynApps (Forte) Mentor Cadence Copyright 2013 Forte Design Systems
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2000 - A Framework for True Open Development of System Standards Is Formed
Multi-party negotiations New license negotiated Truly open governance established Key framework established Legal framework for contribution and licensing Legal framework for collaboration Organizational support for working groups Synopsys Fujitsu Cadence Forte CoWare Mentor ST OSCI Sony NEC ARM Ericsson Motorola Infineon Frontier Open SystemC Initiative established as independent organization June 2000 Copyright 2013 Forte Design Systems
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Fixed-point datatypes
SystemC V June 2000 Sep ‘99 SystemC V0.9 CoWare contributed technology to improve system modeling Frontier contributed technology to improve algorithm modeling CoWare N2C OSCI SystemC V1.1 Jun ‘00 Master-slave channel Frontier A/RT Fixed-point datatypes Copyright 2013 Forte Design Systems
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SystemC Motivations Y-diagram top-down system design
System architecture modeling High-level synthesis Algorithm modeling Frontier data types Copyright 2013 Forte Design Systems
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Fixed-point datatypes
SystemC V April 2000 Sep ‘99 SystemC V0.9 Significant step forward for more abstract modeling Channels Interfaces Events First product of new collaborative development Cadence CoWare Fujitsu Motorola ST Microelectronics Synopsys First solid library implementation CoWare N2C OSCI SystemC V1.1 Jun ‘00 Master-slave channel Frontier A/RT Fixed-point datatypes OSCI SystemC V2.0.1 Apr ‘02 Language Working Group Channels Interfaces Events Copyright 2013 Forte Design Systems
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Fixed-point datatypes
TLM April 2005 SystemC V0.9 CoWare N2C OSCI SystemC V1.1 Jun ‘00 Master-slave channel Frontier A/RT Fixed-point datatypes OSCI SystemC V2.0.1 Apr ‘02 OSCI TLM 1.0 Apr ‘05 TLM 1.0 Established necessary scope concepts, and consensus Didn’t standardize enough to enable interoperability Copyright 2013 Forte Design Systems
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Fixed-point datatypes
SCV July 2006 Sep ‘99 OSCI SCV 1.0 Jul ‘06 SystemC V0.9 CoWare N2C OSCI SystemC V1.1 Jun ‘00 Master-slave channel Frontier A/RT Fixed-point datatypes OSCI SystemC V2.0.1 Apr ‘02 OSCI TLM 1.0 Apr ‘05 Verification Constructs Transaction logging Constrained random data generation Copyright 2013 Forte Design Systems
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SystemC Motivations Y-diagram top-down system design
System architecture modeling High-level synthesis Algorithm modeling Verification Focus of Verification Working Group Copyright 2013 Forte Design Systems
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Fixed-point datatypes
TLM June 2008 Sep ‘99 OSCI SCV 1.0 Jul ‘06 SystemC V0.9 CoWare N2C OSCI SystemC V1.1 Jun ‘00 Master-slave channel Frontier A/RT Fixed-point datatypes OSCI SystemC V2.0.1 Apr ‘02 OSCI TLM 1.0 Apr ‘05 OSCI TLM 2.0 Jun ‘08 TLM-2 Huge collaborative effort on bus modeling Established basis for model interoperability Acts as essential “glue” for almost all Virtual System Platform development Copyright 2013 Forte Design Systems
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SystemC Motivations Y-diagram top-down system design
System architecture modeling High-level synthesis Algorithm modeling Verification Virtual system platform development Emerged as key TLM use model Copyright 2013 Forte Design Systems
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Fixed-point datatypes
SystemC AMS March 2010 Sep ‘99 OSCI SCV 1.0 Jul ‘06 OSCI AMS 1.0 Mar ’10 SystemC V0.9 OSCI AMS 2.0 Mar ’13 CoWare N2C OSCI SystemC V1.1 Jun ‘00 Master-slave channel Frontier A/RT Fixed-point datatypes OSCI SystemC V2.0.1 Apr ‘02 OSCI TLM 1.0 Apr ‘05 OSCI TLM 2.0 Jun ‘08 SystemC AMS Adds Analog constructs to SystemC OSCI SystemC V2.2 Mar‘07 OSCI SystemC V2.3 Jun ‘12 Copyright 2013 Forte Design Systems
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Fixed-point datatypes
SystemC AMS March 2010 Sep ‘99 OSCI SCV 1.0 Jul ‘06 OSCI AMS 1.0 Mar ’10 SystemC V0.9 OSCI AMS 2.0 Mar ’13 CoWare N2C OSCI SystemC V1.1 Jun ‘00 Master-slave channel Frontier A/RT Fixed-point datatypes OSCI SystemC V2.0.1 Apr ‘02 OSCI TLM 1.0 Apr ‘05 OSCI TLM 2.0 Jun ‘08 OSCI SystemC V2.2 Mar‘07 OSCI SystemC V2.3 Jun ‘12 Copyright 2013 Forte Design Systems
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SystemC Use Models Of Interest
Y-diagram top-down system design System architecture modeling High-level synthesis Algorithm modeling Verification Virtual system platform development Analog Focus of Analog Working Group Copyright 2013 Forte Design Systems
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So, where does all that leave us?
Copyright 2013 Forte Design Systems
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SystemC Motivations Y-diagram top-down system synthesis
Still not real Y-diagram top-down system synthesis System architecture modeling High-level synthesis Algorithm modeling Verification Virtual system platform development Analog development Some activity Strong in some geographies and growing Pretty much nowhere A fair amount of use, but not with SCV The biggest use overall Quietly growing Copyright 2013 Forte Design Systems
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Where do we go from here? Copyright 2013 Forte Design Systems
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Source code Interoperability
Where do we go from here? 1. Interoperability between HLS and VSP flows Ability to use HLS source code in VSP When faster VSP source isn’t available For verification VSP HLS Source code Interoperability Copyright 2013 Forte Design Systems
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Mixed-signal SoC Model
Where do we go from here 2. Adoption of other use models? Algorithm design Instead of Matlab? Connected to Matlab? Analog design As part of SoC modeling To model sensors/real world Algorithm design Functional design Digital Models Analog Models Mixed-signal SoC Model Copyright 2013 Forte Design Systems
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Automated & Manual Partitioning
Where do we go from here 3. Top-down system synthesis (finally) SystemC will be at the center of this Model availability Ecosystem Functional design Automated & Manual Partitioning Platform Components Software Synthesis VSP Synthesis Hardware Synthesis Copyright 2013 Forte Design Systems
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