1. Power MOSFET Technical Training
Datasheet Overview
Giovanni Privitera
Senior Product Engineer
MOSFET & IGBT DIVISION

2. Never exceed !!!!!!!!!!!! Maximum Ratings
Represent the extreme capability of the devices.
To be used as worst conditions (single parameter) that the design should
guarantee will not be exceeded. [only VDS & VDGR may be exceeded in limited avalanche conditions]
Never exceed !!!!!!!!!!!!

3. (Rgs to avoid floating gate)
The avalanche breakdown voltage of ST’s PowerMOSFET is always higher than its voltage rating due to normal production process margins.
For the Drain-Gate
Voltage capability
(Rgs to avoid floating gate)
In order to achieve high forecasted reliability the worst case operating voltage should be lower than the maximum one. The maximum voltage during turn off should not exceed 70 to 90% of the rated voltage. This derating is suggested by the years of experience.

4. Exceeding Vgs may result in permanent device degradation due to
oxide breakdown and dielectric rupture.
The real oxide breakdown capability is higher than this value, and is related to the oxide thickness;
but this value, with a reasonable guardband, is the 100% TESTED & warranted one

5. Reflects a minimum device service lifetime.
The majority of reliability tests are done at maximum junction temperature, especially the HTRB (High Temperature Reversed Bias) and HTFB (High Temperature Forward Bias). These test results are used as input information for calculation of acceleration factors in different reliability models. In order to achieve high forecasted reliability the maximum operating temperature should be lower than the maximum one. For example, by theoretical models, reducing the junction temperature by 30°C will improve the MTBF (Mean Time Between Failure) of the MOSFET by an order of magnitude.
Tj must be always lower than 150ºC
Reflects a minimum device service lifetime.
Operation at conditions that guarantee
a junction temperature less than Tjmax
may enhance long term operating life.
Ptot=dT/Rthjc=(150-25)/Rthjc
derating=1/Rthjc

6. I= (Tjmax-Tc)/Ron(@Tjmax)/Rthjc
Limited by Ptot & Rdson
Ptot = (Tjmax-Tc)/R
THj-c I=
Limited also by wire size : to avoid any fuse effect

8. To be distinguished two kind of dv/dt (static and dynamic)
Maximum dv/dt capability during diode reverse recovery (dynamic dv/dt)
To be distinguished two kind of dv/dt (static and dynamic)

9. b) Parasitic transistor turn on
Due to the false turn-on, the device falls into the current conduction state, and in severe cases, high power dissipation develops in the device and creates destructive failure.
Static dv/dt
a) False turn on
b) Parasitic transistor turn on
If the parasitic bipolar transistor is turned on, the breakdown voltage of the device is reduced from BVCBO to BVCEO which is 50 ~ 60 [%] of BVCBO . If the applied drain voltage is larger than BVCEO, the device will be brought into the avalanche breakdown, and if the drain current cannot be limited externally, the device could be destroyed by the second breakdown of parasitic bipolar.

10. Diode recovery dv/dt Highest Stress point
The value of di/dt and dv/dt becomes larger as Rg is reduced.
The device is destroyed by the simultaneous stresses such as high drain current, high drain source voltage and the displacement current of the parasitic capacitance.
Highest Stress point

11. ST insulated packages are tested 100% to guarantee this value.

14. Thermal resistance Thermal chain exists from the
silicon to the ambient through
the die attach, the frame, the
contact and the external
dissipator. R
THj-a =R
THj-c +R
THc-s
THs-a
Thermal model for transient takes
into account thermal capacitances

15. Allowed but not reachable region
Rthjc=1/0.32=3.1 K/W
K=1
K=0.1
Zth=kRth
V I=(Tj-Tc)/Zth
K=0.04
K=0.01
Allowed but not reachable region

16. Iar, defined as the maximum current that can flow through the device during the avalanche operations without any bipolar latching phenomenon.
EAS (Energy during Avalanche for Single Pulse) is defined as the maximum energy that can be dissipated in the device during a single avalanche operation, at the Iar and at the starting junction temperature of 25°C, to bring the junction temperature up to the maximum one stated in the absolute maximum ratings.

17. Unclamped Inductive Switching2
E=0.5*L*I
*(V(BR)eff/(V(BR)eff-VDD))
E=0.5*V(br)eff*Io*tav

18. Failure mode P+ N- N+ G D S Rp S D G Id
Vbe
1-As soon as the current begins to interest the p region causing a sufficient drop of voltage to equal the VBEon of the BJT, the current of the base, IB, in conjunction with the  of the transistor will cause the localized BJT turn-on. Subsequent local temperature increase decreases Vbeon and runaway occurs.
2-The power that is dissipated in the MOSFET causes an increase of temperature of the junction. If the temperature increases to a critical value set by the property of the silicon, the failure, without the contribution of the parasitic bipolar, occurs because of the creation of thermally generated carriers in the epitaxyal / bulk region and so the creation of hot spots.

19. Eas calculation: thermal model
Very short rectangular pulses (~tens ms)
Die Area
Triangular impulses haven’t the same thermal response
time Tj

20. The EAS is function of Die size Silicon characteristics Peak power
Starting and maximum temperature
with

21. Current Crowding due to Parasitic BJT Turn-on
Thermal Dissipation with Tj highly exceeding the guaranteed Tjmax (150 degC)

22. As junction temperature increases, BV also increases linearly,D S G
Tracer waveform
As junction temperature increases, BV also increases linearly,

23. D S G
IDSS is sensitive to the temperature and it has positive temperature coefficient.

24. D S G

25. VGS(th) has a negative temperature coefficientD S G
Threshold voltage VGS(th) is the minimum gate voltage that initiates drain current flow.
VGS(th) has a negative temperature coefficient

26. RDS(on) is not constant vs IdG
RDS(on) is not constant vs Id
RDS(on) has a positive temperature coefficient

27. D S G
Gfs=
dids
dvgs
Vds=const T

28. Temperature variations have very little effectD S
CGS
CDS
CGD
Ciss = CGD + CGS
Coss = CDS + CGD
Crss = CGD G
Temperature variations have very little effect

29. Resistive load switching

30. Resistive load switching
IDS [A] 6 5 4
VG=0 3 VD 2 1
ID=0 1 2 3 4
500
VDS [V] 68

31. Resistive load switching
IDS [A] 6
Charging the Ciss to Vth.
No evident drain current flows;
Vds remains essentially at Vdd 5
VG= VTh 4
VG=0 3 VD 2 1
ID~0 1 2 3 4
500
VDS [V] 1 69

32. Resistive load switching
IDS [A] 6
Continues the Ciss Charging.
Drain current starts to flow;
Vds remains essentially at Vdd 5 VT 4
VG=0 3 VD 2 1
ID=0 1 2 3 4
500
VDS [V] 1 2 70

33. Resistive load switching
IDS [A] 6
Continues the Ciss Charging.
Drain current flows to the maximum;
Vds remains essentially at Vdd
VG= VGm 5 VT 4
VG=0 3 VD 2 1
ID=0 1 2 3 4
500
VDS [V] 1 2 71

34. Resistive load switching
IDS [A] 6
Cgd is Charging and Ciss increases mantaining Vg flat. Id constant
Vds approaches to Vdson
VG= VGm 5 VT 4
VG=0 3 VD 2 1
ID=0 1 2 3 4
500
VDS [V] 1 2 4 73

35. Resistive load switching
IDS [A] 6
MOSFET in ohmic region.
Vg increases to applied voltage charging input capacitances 5 VT 4
VG=0 3 VD 2 1
ID=0 1 2 3 4
500
VDS [V] 1 2 4 74

36. Resistive load switching
IDS [A] 6 5 VT 4
VG=0 3 VD 2 1
ID=0 1 2 3 4
500
VDS [V] 1 2 4 75

37. Resistive load switching
IDS [A] 6 5 VT 4
VG=0 3 VD 2 1
ID=0 1 2 3 4
500
VDS [V] 1 2 4 76

38. It is used to determine the amount of charge,
defined as Qg, required to bring the Ciss from 0V to 10V
10V D S G

39. Qrr~0.5 trr*Irrm
ISD
Irrm