1. Flopoco in LegUp
Jenny deng

2. Motivation
LegUp currently depends on Altera IP cores for floating point operations
Limited to Altera FPGAs, restricts user base
Open-source floating point cores would extend functionality to other families
Gives LegUp greater flexibility

3. About Flopoco
Flopoco – open-source tool for generation of arithmetic cores
Takes operator specifications as input, outputs synthesizable VHDL
Requires mixed language simulation
Parameterized with:
Target family (Cyclone, Stratix, Virtex)
Target frequency
Operator bitwidths
Floating point, fixed point, conversion operators

4. Performance vs Altera Tested Flopoco add, multiply, divide operators
Synthesized in Quartus II
Compared results with existing Altera cores

5. Implementation in LegUp: Preparation
Manually substituted Flopoco modules into LegUp generated code first
Challenges:
Flopoco has its own floating point format – requires converters to IEEE standard
Addition of converters interfered with signals in some operators
Renamed ports and signals to correspond to Altera cores
Generated operators pipelined to same depth

6. Implementation in LegUp: Execution
Worked on flattened hierarchy branch
Option to share modules across functions
Created support for floating point operations
Added in library of Flopoco operators
No corresponding operators for extend, truncate, compare found
Combined existing converters to create extend and truncate
Wrote compare

7. Implementation in LegUp: Execution
Switch between the two with tcl parameter USE_FLOPOCO
Turn on module sharing with tcl parameter SHARE_FPFU_BETWEEN_FUNCTIONS
Compare operator not bound – must instantiate separate modules
Created three new testbenches
Created separate Flopoco example directory

9. Results Both Altera and Flopoco pass all testbenches in simulation
Cycle counts are identical

10. Next Steps In the process of code clean-up and merge
Generate Fmax and area results for comparison
For the future: implement complete math library
Not supported by Flopoco