1. TUTORIAL: Digital-on-Top
Alberto Stabile

2. Conventional flow Write a behavioral design (VDHL or Verilog)
Set-up of input files for the synthesis
Synthesis (generation of RTL Verilog)
Set-up of input files for the P&R
Encounter floorplan (requires a lot of time depending on the complexity of design)
Liberty files from analog block (to describe timing arc and power consumption)
LEF file from analog block (to describe the layout geometries)
Foundation Flow in Encounter
See next slide

3. Foundation flow (place & route)

4. Complex designs like amchip06: Place & Route (Backend) approach
Hierarchical approach (bottom up)
needed to reduce computation time
Two main block exists:
2k-patterns block placed 64 times
top block without 2k pattern
Three place & route flow are needed:
2k-pattern block
top block w/o 2k block
assembled design

5. Digital simulations
Digital simulations are required pre and post Encounter with backannotate SDF delays to validate the functionality of chip

6. Signoff verification Timing MUST be improved with Tempus
IR drop must be check with Voltus
VerifyConnectivity and VerifyGeometries are two useful function to check the final layout
LVS & DRC must be runned with Virtuoso

7. Strong approach Repetitive block design by hand
Complex logic or timing design with automatic systems

8. Synthesis example with rc
Alberto Stabile

9. Set up the input file
First, we have to decide which LEF and LIB file use of the technology
The chose is not simple because there are a large number of option (for more detail please ask off-line)
Create a tcl file (a script) to use for the synthesis
Here we have to create «pointers» to the technologies files (LIB and LEF) and also, if we have, our LIB & LEF files.

10. LAB EXERCISE
Please connect to our account on olorin.fisica.unimi.it via VNC
We have different VNC
Navigate on FrontEnd folder
Open the file named run_synthesis_withRc.tcl

11. Synopys Design Constraint file
It is a standard to limit the design within same pre-decided constraints.
Also used for the FPGA timing
A lot of user manual online:
design-constraints-guide

12. LAB EXERCIse
If you run correctly the RC you will have a folder named output*
Inside this folder we will check the .sdc and the .v files
These files will be used to the P&R

13. Foundation flow
A. Stabile

14. Foundation flow (place & route)

15. LAB EXERCIse
Open encounter and generate all files need to generate the scripts
The setup.tcl file is the core of settings
Check out the EDI folder
Questions?

16. LAB EXERCIse Run make init Open cadence at the end of init step
Start the design of floorplan
Questions?