1. “FPGA shore station demonstrator for KM3NeT”by
K. Manolopoulos, A. Belias and B. Koutsoumpos
NESTOR Institute - NOA
Presenting for the KM3NeT Consortium: Kostas Manolopoulos

2. KM3NeT Readout Concept KM3NeT: Deep sea neutrino telescope
More than 10,000 optical modules
Point to point optical network
Numerous optic fiber channels arriving at the shore station
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K. MANOLOPOULOS, NESTOR Institute

3. Resulting Requirements
Shore station requirements:
Receive incoming data
Perform merging and time ordering
Send data to DAQ system
Transmit necessary commands to the optical modules
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4. Overall Readout Scheme
All digitized data sent to shore
Expected rate > 100Gbps
Real-time processing
Bidirectional functionality
Asymmetric physical channel allocation
K. MANOLOPOULOS, NESTOR Institute

5. KM3NeT Demonstrator 4 Digital Optical Modules (DOMs) Shore station
Convert measurements to digitized data
Transmit them embedded in an Ethernet frame to the shore
Shore station
collects incoming data
issues commands to DOMs
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6. Readout Electronics on Shore
Main functions:
Ethernet point to point data reception
Ethernet broadcasting data distribution
Clock & Synchronous Command distribution
Time measurement of the optical network for each point  (calibration)
GPS reference time stamping interface
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7. Shore Station Functional diagram
Optical Network
Optical
Domain
Ethernet
Switch
GPS & Clock services Rx Tx
SMA
ML605
ML507
SFP
DAQ
see talk by Anvar Shebli
see talk by
Jelle Hogenbirk
PCI / FMC connections
SMA cable
RJ45 Ethernet cable
SC link (I2C)
Ethernet cable
K. MANOLOPOULOS, NESTOR Institute

8. ML605 Block diagram Clk &Command Control Master clock TEMAC
GTX
Buffer
Clk &Command
Control
Time system
(Counter, etc..)
Clk & Cmd
Extraction
Insertion
Master clock
TEMAC
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9. Xilinx ML605 Evaluation Board
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10. ML605 Characteristics FPGA: VIRTEX 6 LX240T-1
Communications & Networking
10/100/1000 Tri-Speed Ethernet (GMII, RGMII, SGMII, MII)
SFP transceiver connector
GTX port (TX, RX) with four SMA connectors
4 hard TEMAC cores
K. MANOLOPOULOS, NESTOR Institute

11. ML605 Characteristics 20 GTX Multi Gigabit Transceivers
8 MGTs wired to PCIe
8 MGTs wired to FMC HPC connector
Clocking resources
200 MHz Oscillator (Differential)
SMA Connectors for external clock (Differential)
K. MANOLOPOULOS, NESTOR Institute

12. PCI Express Expansion Module
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13. Quad SFP Transceiver
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14. Xilinx ML507 Evaluation Board
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15. ML507 Characteristics FPGA: Virtex 5 FX70T-1
Programmable system clock generator
10/100/1000 Tri-Speed Ethernet
PCIe with 1 GTP/GTX
SFP transceiver connector with 1 GTP/GTX
Same processor as in DOMs
Runs DAQ software in VxWorks
(see talk by Frederic Louis)
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K. MANOLOPOULOS, NESTOR Institute

16. Conclusions So far we have: What next?
developed an architecture for data gathering and broadcasting
evaluated FPGA based platform systems for the shore station
full-chain test coming up
What next?
Adapt the existing scheme to actual KM3NeT scale
Enhance it with respect to flexibility and scalability
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K. MANOLOPOULOS, NESTOR Institute

17. Thank you for your attention. Questions?
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K. MANOLOPOULOS, NESTOR Institute

18. Backup slides
K. MANOLOPOULOS, NESTOR Institute