1. NanoCMOS Effects and Analogue Circuits University of Edinburgh
Statistical Design and Verification of Analogue Systems
NanoCMOS Effects and
Analogue Circuits
University of Edinburgh
Wolfson Microelectronics

2. MOSFETs as analogue devices Static nano-effects Dynamic nano-effects
Agenda
MOSFETs as analogue devices
undergraduate level!
Static nano-effects
Dynamic nano-effects
Drift
… all as “cartoon-physics”

3. “Normal” MOSFET Met Met Met Poly Vgs>Vt P- N+ N+
Doping is (here, exceptionally!) uniform

4. “Normal” MOSFET Met Met Met Poly P- N+ - N+ - - - - - <v>
Terminal velocity … cf swimming through porridge
<v>

5. “Normal” MOSFET
Saturated On
Off
Linear
Interactive MOSFET curves

6. Nanoscale MOSFET P-
Poly
Met N+

7. Nanoscale MOSFET P-
Poly
Met N+
c10-9M

8. Nanoscale MOSFET Crash sites Sources of statistical variability
Random discrete dopants
Line Edge Roughness
Grains in polysilicon
Combined

9. Device number 1 Nanoscale MOSFET Met Met Met Poly P- N+ N+ -
crash sites -
Device number 1

10. Device number 2, next door
Nanoscale MOSFET
Met
Met
Met
Poly P- N+ N+ - -
Device number 2, next door

11. Nanoscale MOSFETs - mismatch
These devices are NOT THE SAME
Nothing can make them the same, short of placing the dislocations, impurities and dopant atoms by hand and identically in every device
The mismatch is intrinsic -

12. Nanoscale MOSFET
Interactive MOSFET curves

13. Nanoscale MOSFET Current Mirror, Iin = Iout

14. Nanoscale MOSFET – solutions#1 - overdesign
Iin
Iout

15. Nanoscale MOSFET – solution#2?
Iin
Iout
Iin
Iout Vt  Vt
nanoscale variation of Vt, K’ 
Systematic variation of Vt, K’
X (distance)

16. Trapping in MOSFETs
Met
Met
Met
Poly P- N+ N+ - - - -
trap
release

17. Many traps, micro-scale device
Flicker noise
Many traps, micro-scale device
Constant succession of trapping and detrapping
Flicker noise I t

18. Nanoscale MOSFET
Interactive MOSFET curves

19. nanoscale … Random Telegraph Signal noise
Few traps, nano-scale device, discontinuous
Sudden discontinuities in Ids
hence “Telegraph Signal “
Ids t

20. Nanoscale MOSFET I2 I1

21. no trapped charge with trapped Random doping I-V curve extraction
2 compact models
(BSIM4) per device
no trapped
charge
with trapped
Random doping
I-V curve
extraction

22. Method – single trap Initialise trap states and bias conditions
Two compact models: 1) trap filled 2) trap empty
Select model (1) or (2)
Initialise circuit
SPICE simulation
Store SPICE nodal voltages
Recalculate trap occupancy based o probability of trapping

23. 4-quadrant multiplier

24. 4-quadrant multiplier

25. Single RTS-noisy MOSFET

26. 30x RTS-noisy MOSFET

27. Negative Bias Temperature Instability (NBTI) Effects
Met
Met
Met
Poly
V<0 E N- P+ P+ + + E
Vdd
Vgs<Vdd
E→E – E
Trapped charge works against Vgs
E-field causing inversion is reduced
Threshold Vt is raised

28. Negative Bias Temperature Instability (NBTI) Effects
Most prevalent in pMOS devices
when a negative voltage is applied to the PMOS gate
this is the “stress voltage”
Capture of positive charge carriers (holes)
at the Si-SiO2 interface
→ positive (trapped) charge
Threshold Voltage Vt is raised
Removal of the stress removes some traps
partial recovery

29. Negative Bias Temperature Instability (NBTI) Effects
Vt of pMOSFETs at different temperatures (500MHz, Vdd = 1.2).