1. What do they mean? How do we test them? Op Amp Specifications
Keith Kendall & Bruce Trump
Including Portions from the
Bruce Trump & Gina Hann 2-Op Amp Loop Presentation
(As of 2004/09/11 4 PM 40 slides)
We will also cover common test circuits.
(Why are these things important to the customer?)

2. Is he done yet? How we Choose specifications (the tests)
Absolute Max Ratings
Electrical Specifications
Input Offset – introducing the Two Op Amp Loop
Open Loop Gain
Output Voltage Swing
Common Mode Rejection Ratio
Vos revisited
Power Supply Rejection Ratio
Input Bias Current & Input Offset Current
Another test circuit – the False Summing Junction
Life Test
Thermal Drift
Typical Curves
System Generated Ordering Table the “Package Option Addendum”
Your Turn

3. Typical Tests One Limit Upper and Lower Limit
ISC Short Circuit Current
CMRR(2)
IO Output Current
PSRR(2)
IQ(1) Quiescent Current
IB(2) Input Bias Current
VOH Output High Voltage
IOS(2) Input Offset Current
VOL Output Low Voltage
VOS(2) Input Offset Voltage
AOL
Tested as two sided
We usually ignore the sign
I divide them up into one sided and two sided because it makes a difference in yield.
In fact there isn’t even general agreement on what the how to define the polarity of Vos.
All the two sided tests (except for the input current tests) use the same test circuit.

4. Gaussian (or Normal) Distribution
68% within ±1 standard deviation
99.7% within ±3 standard deviations
Statistical process control techniques are based upon the assumption that the distribution is normal.
We want good yield.
If we are going to have a high grade…
Production must have tested millions of parts to get a curve this symmetrical. (actually it’s a fake distribution)
Median here is to get the chart to look nice.
St Dev=12.5; (95.4% within 2 stdev)
It would be nice to have the Standard deviation lines come in later, but they are part of the picture.

5. Yield per test at various sigma
We want a decent test yield. What limits do we need to choose to get an appropriate yield?
“Six Sigma is commonly defined as 3.4 defects per million opportunities.”
Dramatic decrease

6. Production Worthy Test Limits
We do not just test one parameter, we test many parameters
Illustrates the necessity of setting test limits wide enough
Compound Yield
Let’s assume that all the parameters are normally distributed, the process is in control, and that the limits are all set to the stated number of standard deviations.
Cont, Iq, Vos, CMRR, PSRR, Aol, Swing, Ib+, Ib-, Ios, Isc = 11 tests

7. Cover Page, the device at a glance
I look at the cover page to get an overview about the device.
? Does this obviate the need for the Product Bulletin?

8. OPA380 Absolute Maximum Ratings
OPA V part
Ensure that the device isn’t subjected to any stress beyond these.
The user must either limit the input current or the input voltage.
ESD rating. In the past you had to contact Product Marketing

9. Vos: What is it? DUT +1mV 1mV-
DUT
+1mV +
VOS
1mV
For our purposes let’s define VOS as follows:
If it produces a positive voltage on the output in this circuit, then Vos is positive.

10. Vos Measurement… simple method-
DUT
1000·VOS
= 1V +
VOS
1mV
-2.5V
How about this for a test circuit.
If I was ask to come up with a test circuit for Vos, I would have came up with something like this.
When you realize that Vos varies depending on the output, it becomes clear that this circuit is not a good test method.

11. Vos is not a constant VOS VOUT -2 -1 0 1 2
All specifications at TA = +25°C, RL = 2kΩ connected to VS/2, VOUT = VS/2, and VCM = VS/2, unless otherwise noted.
VOS
VOUT
It is specified for Vout = mid-supply
In the rest of this presentation we will talk a lot about Vos
It is significant in CMRR, PSRR, and Aol

12. Vos Measurement… simple method-
DUT
1000·VOS +
VOS
-2.5V
Includes error component due to Open-Loop Gain
The measurement will include an error because of the finite gain of the Op Amp.
Disadvantages
- The finite gain has an effect
- The output isn’t at zero volts (open loop gain error)

13. The Two Op-Amp Loop R1
999R1
+2.5V
DUT - +
VOS A2
-2.5V
1000·VOS
Loop controls DUT’s output voltage at accurately defined potential. (0V)
Here is a simplified schematic similar to a circuit that we often use in test
+ Does not load the DUT
+ Low Aol DUTs work just fine
+ Can easily force the DUT output to any value within it’s range
- High component count
- Typically needs compensated for stability

14. Compensating the Two Op-Amp LoopOR R1
999R1
DUT - +
VOS A2
1000·VOS
Inputs to both op amps are reversed. Feedback remains the same, but the loop is more easily compensated.
Either way will work fine.
(Alternating animation)

15. Open Loop Gain (AOL) AOL = ΔVOUT / ΔVOSR1
999 R1 V+
VOUT
DUT - +
VOS A2
1000 · VOS V-
Max Vout +
VOUT -
Modulate VOUT control signal between VMAX and VMIN
Min Vout
Again, the same test circuit with a minor change.
Subject to the limitation of the Op Amp, the driving node forces the output to whatever value we desire.
Then we can measure the input offset throughout the range of possible output voltages.

16. Offset voltage rapidly increases as output tries to swing to rails.
Open Loop Gain (AOL)
Offset voltage rapidly increases as output tries to swing to rails.
VOS
VOUT V- V+

17. Open-Loop Gain is 1/Slope between end-points (in dB).
Open Loop Gain (AOL)
VOS
VOUT
Open-Loop Gain is 1/Slope between end-points (in dB).
Max
Vout
Min
AOL = ΔVOUT / ΔVOS
Tradeoff – We struggle to set the test limits.
(We want a wide specified range, but the wider the voltage range, the lower the open loop gain.)

18. Output Voltage Swing .
Slam Test

19. Common Mode Rejection Ratio
Make loop control Vout
to be at mid-supply.
+2.5V R1
999R1
DUT - +
VOS A2
1000 · VOS
VOUT = “Mid-Supply” = 0V
-2.5V
? Why is this slide in here?
? Could we eliminate this slide?
? Do we care about mid supply when we test it?

20. Common Mode Rejection Ratio
5.1V
CMRR test part 1 of 2
CMRR = ΔVOS / ΔVCM R1
999R1
DUT - +
VOS A2
1000 · VOS
0.1V
VOUT = “Mid-Supply” = 2.6V
It is a trick. Instead of moving the input, we are moving the supply.
Emphasize MID-SUPPLY

21. Common Mode Rejection Ratio
CMRR test part 2 of 2
CMRR = ΔVOS / ΔVCM
-0.1V R1
999R1
DUT - +
VOS
1000 · VOS
VOUT = “Mid-Supply” = -2.6V
The difference
-5.1V

22. Common Mode Rejection Ratio
CMRR = ΔVOS / ΔVCM
Transition Region
Between two input stages
VOS V- V+
VCM
N channel typically kicks in at 1.5 to 1.8 V below V+

23. Common Mode Rejection Ratio
CMRR = ΔVOS / ΔVCM
CMRR is slope of line between end-points (in dB).
VOS V- V+
VCM
Min CM
Max CM

24. Common Mode Rejection Ratio
CMRR = ΔVOS / ΔVCM
Half Scale provides smaller (better) ΔVCM/ΔVOS ratio
VOS
For devices with RR inputs we often provide a second CMRR spec for only the lower input stage. V- V+
VCM
On trimmed parts we trim both N-channel and P-channel which minimizes the crossover distoriton.
OPA363, OPA364, OPA365 don’t have this discontinuity (Crossover distortion)
Min CM
Max CM

25. R/R Input without Transistion
We covered Vos earlier, but now that we have talked about how CMRR is affected by the transition region the difference between most RR Op Amps and those without a transition region it is worth looking at again since it is so central to CMRR.
The OPA363/364 is a 1.8 to 5 volt part. The problem is more dramatically visible at lower supply voltage.
(and the OPA365 which is in development 1.8V, 50MHz low noise, low Iq; 2H2005)

26. Power Supply Rejection Ratio
PSRR test part 1 of 2
PSRR = ΔVOS / ΔVS
Min Supply R1
999 R1
+1.85V
DUT - +
VOS A2
1000·VOS
-0.85V
Does this circuit look familiar?
Simplified, conceptual
How does the customer use it? With the inputs at mid supply? With the inputs at the most negative rail?

27. Power Supply Rejection Ratio
PSRR test part 2 of 2
Max Supply
PSRR = ΔVOS / ΔVS
+3.25V R1
999 R1
DUT - +
VOS A2
1000·VOS
-2.25V

28. Power Supply Rejection Ratio
VOS vs. VS
VOS(μV)
“Soft” breakdown at high voltage.
Operation “falling out”
at low voltage.
Total Supply Voltage
We include PSRR vs. Frequency and CMRR vs. Frequency in out data sheets.

29. Power Supply Rejection Ratio
At TA = +25°C, RL = 10kW connected to VS/2 and VOUT = VS/2, unless otherwise noted.
VOS(μV)
Max Vs
Min
PSRR is slope over end-points.
120 90 60 30
-30
-60
-90
-120
PSRR = ΔVOS / ΔVS
? At min Vs the Aol falls off
? At max Vs soft breakdown
Total Supply Voltage

30. Input Bias Current Test Circuit
IB = ΔVos / 1M
It is the same as the 2 Op Amp loop with resistors added in series with the inputs in order to measure the input current.
Both inputs
This circuit works fine for circuits with Ib>1nA

31. Input Bias Current Test Circuit Charge accumulationV 20 15 10 5
(ms)
TIME
IB = C*dVc/dt
Example: IB = 1nF*5mV/10ms = 50pA
Useful for CMOS where leakage currents are very small

32. Input Offset Current, IOS
Input Offset Current is the difference between the two input bias currents.
IOS = (IB+) - (IB-)
It is a calculated value

33. The False Summing Junction
= 101 * Vos
Vref is based on the desired output voltage
Vout = 101 * Vos when Vref is ground
There is another means of testing all of these Vos based parameters – the false summing junction.
The resistor divider multiplies errors so they are easier to measure.
Basically it is used the same was as the two Op Amp loop
WHY WE HAVE THE DIVIDER
+ More stable than 2 Op-amp loop
+ Low component count; resulting in a compact layout
± Swing depends on Vos – just measure Vos first
- Loaded test
- Low Ib required (Ios canceled Op Amps are not a problem)
- High Aol required

34. Life Test Different groups – Different criteria
Allow a shift of <10% of the data sheet range
Allow 50% of the data sheet range for Vos and certain others
1.5
1.0
0.5
-0.5
-1.0
-1.5
For Example a device with a Vos specification limit of ±1mV
? What about PSRR, CMRR, Aol

35. Thermal Drift Example VOS Drift Measurement DUT -40ºC 25ºC 85ºC
A mV
B mV
C mV
Drift Calculation
A = ( ) / 125 = 0.05mV/ºC
B = ( ) / 125 = 0.05mV/ºC
C = ( ) / 125 = 0.05mV/ºC
Drift = ( |slope1| + |slope2| ) / TempRange
We characterize over the temperature range, then typically do production drift at 3 temperatures.
Averaging

36. A Curve as found in the data book
Looks good – a nice smooth curve showing how current varies with temperature.

37. How about Worst Case?
Typical curves show how the parameter usually varies, but typical is not worst case.

38. System Generated Ordering Table
It doesn’t require the data sheet to be updated for this information to change. May be different from the data sheet since this is a live page.
Look for it.
All new data sheets, and many of the older ones have it.

39. The Future System Generated Ordering Table
09/02 Sent inquiry to learn when this will happen. Answer – the implementation date is not yet decided. Per Jim Marr 9/2
There is a potential for confusion here, since the package type listed here is very generic, and often different from what we list at the front of the data sheet.
We call the DBV package a SOT23-3, SOT23-5, SOT23-6.
(The DBC is either a typo, or a new creation that is not yet listed as a TI package.)

40. The End
Your Turn to talk