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Chapter 5: A Multi-Cycle CPU.

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Presentation on theme: "Chapter 5: A Multi-Cycle CPU."— Presentation transcript:

1 Chapter 5: A Multi-Cycle CPU

2 The Multi-cycle idea... We can use any logic block once each cycle
PC Read address Read reg. 1 Read data 1 Memory Read reg. 2 Read data Registers Result Write address Write reg Read data 2 Write data Write data Memory: Holds Instructions Holds Data ALU: Computes R-type value Computes Address Computes next PC Computes Branch Registers: Hold data values

3 Multi-cycle Datapath Update PC=PC+4 Load Instruction:Need address
Read Instruction from memory Decode,Read registers (R-type) Start: PC Do ALU Op PC 1 PC 1 Memory Read address Write address Write data Read data [25-21] Result Zero Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A [20-16] 1 [15-11] 1 2 3 4 1 Write Result reg. sign extend Sh. Left 2 16 32 Branch [15-0] Read from Memory Write result Store Instr.

4 Breaking instructions into cycles
Mem ALU Note: Some of these are unneeded, but they don’t hurt! Instruction Fetch, Increment PC Decode Instruction, Access Registers Jump Reg Update PC Compute Branch Target ALU LW,SW ALU Branch R-type Compute Memory Address ALU If condition holds update PC to Target Execute Instruction ALU Mem Read/Write Memory Write Register Reg Can use each major block (ALU,reg,mem) once each cycle Reg Write Register LW

5 Multi-cycle Control Note: The control signals will be constant during each cycle, but may change during the multi-cycle instruction Control ALUOp IorD Inst[31-26] ALUSelB MemRead MemWrite MemToReg RegDest RegWrite ALUSelA PC PC 1 1 [25-21] Result Zero Memory Address Write data Read data Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A [20-16] 1 [15-11] 1 2 3 4 1 sign extend Sh. Left 2 16 32 ALU control [15-0] [5-0]

6 Issues 1. Memory reads overwrite the instruction - Add Instr. Reg.
2. ALU overwrites PC every cycle - Add PCWrite Signal PCWrite Add PCWriteCond Signal Control 3. Branches? PCWriteCond Zero ALUOp IorD Inst[31-26] ALUSelB MemRead MemWrite IRWrite MemToReg RegWrite ALUSelA RegDest PC PC 1 1 [25-21] Result Zero Memory Address Write data Read data Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A [20-16] Instr. Reg Instr. [31-0] 1 [15-11] 1 2 3 4 1 sign extend Sh. Left 2 16 32 ALU control [15-0] [5-0]

7 Issues On branches, the PC is always written with Zero!
Sh. Left 2 26 28 Concat. PCSource 32 PCWrite Control 4 PCWriteCond 2 1 Zero ALUOp Inst[31-26] IorD Inst[25-0] [31-28] MemRead Logic for Jumps MemWrite ALUSelA IRWrite MemToReg RegDest RegWrite PC or PC+4 PC 1 1 [25-21] Result Zero Memory Address Write data Read data Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A [20-16] A Instr. Reg Instr. [31-0] ALU Out 1 ALUSelB [15-11] B 1 2 3 4 MDR 1 ALU Out: Save result of ALU for use on next cycle MDR: Save result of read for use on next cycle A, B: Save registers for use on next cycle sign extend Sh. Left 2 16 32 ALU control [15-0] [5-0]

8 Instruction Fetch 1 x 1 1 x x 1 Cycle 1 All instructions
Sh. Left 2 26 28 Concat. PCSource 32 1 PCWrite x Control 4 PCWriteCond 2 1 Zero ALUOp IorD Inst[31-26] Inst[25-0] [31-28] MemRead 1 1 x x MemWrite IRWrite MemToReg RegDest RegWrite ALUSelA PC or PC+4 PC 1 1 [25-21] Result Zero Memory Address Write data Read data Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A [20-16] A Instr. Reg Instr. [31-0] ALU Out 1 ALUSelB 1 [15-11] B 1 2 3 4 IorD=0 MemRead=1 MemWrite=0 IRWrite=1 ALUSelA=0 ALUSelB=1 MDR 1 ALUOp=00 PCWrite=1 PCSource=0 RegWrite=0 sign extend Sh. Left 2 16 32 ALU control [15-0] [5-0]

9 Instr. Decode/Reg. Fetch
Cycle 2 All instructions Sh. Left 2 26 28 Concat. PCSource 32 x PCWrite Control 4 PCWriteCond 2 1 Zero ALUOp x IorD Inst[31-26] Inst[25-0] [31-28] MemRead x x MemWrite IRWrite MemToReg RegDest RegWrite ALUSelA PC or PC+4 PC 1 1 [25-21] Result Zero Memory Address Write data Read data Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A [20-16] A Instr. Reg Instr. [31-0] ALU Out 1 ALUSelB 3 [15-11] B 1 2 3 4 MDR 1 MemRead=0 MemWrite=0 IRWrite=0 ALUSelA=0 ALUSelB=3 ALUOp=00 PCWrite=0 PCWriteCond=0 RegWrite=0 sign extend Sh. Left 2 16 32 ALU control [15-0] [5-0]

10 R-type Execution x 2 x x x 1 Cycle 3 R-Type
Sh. Left 2 26 28 Concat. PCSource 32 PCWrite Control 4 PCWriteCond 2 1 2 Zero ALUOp x IorD Inst[31-26] Inst[25-0] [31-28] MemRead x x MemWrite IRWrite MemToReg RegDest RegWrite ALUSelA PC or PC+4 1 PC 1 1 [25-21] Result Zero Memory Address Write data Read data Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A [20-16] A Instr. Reg Instr. [31-0] ALU Out 1 ALUSelB [15-11] B 1 2 3 4 MemRead=0 MemWrite=0 IRWrite=0 ALUSelA=1 ALUSelB=0 MDR 1 ALUOp=10 PCWrite=0 PCWriteCond=0 RegWrite=0 sign extend Sh. Left 2 16 32 ALU control [15-0] [5-0]

11 R-type Completion x x x x 1 1 x x Cycle 4 R-Type MemRead=0 MemWrite=0
Sh. Left 2 26 28 Concat. PCSource x 32 PCWrite Control 4 PCWriteCond 2 1 x Zero ALUOp x IorD Inst[31-26] Inst[25-0] [31-28] MemRead x 1 1 MemWrite IRWrite MemToReg RegDest RegWrite ALUSelA PC or PC+4 x PC 1 1 [25-21] Result Zero Memory Address Write data Read data Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A [20-16] A Instr. Reg Instr. [31-0] ALU Out 1 ALUSelB x [15-11] B 1 2 3 4 MemRead=0 MemWrite=0 RegDest=1 MDR 1 PCWrite=0 PCWriteCond=0 RegWrite=1 MemToReg=0 sign extend Sh. Left 2 16 32 ALU control [15-0] [5-0]

12 Branch if Equal 1 1 1 x x x x 1 Cycle 3 BEQ
Sh. Left 2 PCSource 1 26 28 Concat. 32 PCWrite 1 Control 4 PCWriteCond 2 1 1 Zero ALUOp x IorD Inst[31-26] Inst[25-0] [31-28] MemRead x x x MemWrite ALUSelA IRWrite MemToReg RegDest RegWrite PC or PC+4 1 PC 1 1 [25-21] Result Zero Memory Address Write data Read data Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A [20-16] A Instr. Reg Instr. [31-0] ALU Out 1 ALUSelB [15-11] B 1 2 3 4 MemRead=0 MemWrite=0 ALUSelA=1 ALUSelB=0 PCSource=1 MDR 1 ALUOp=01 PCWrite=0 PCWriteCond=1 RegWrite=0 sign extend Sh. Left 2 16 32 ALU control [15-0] [5-0]

13 Jump 2 1 x x x x x x x x Cycle 3 Jump MemRead=0 MemWrite=0
Sh. Left 2 26 28 Concat. PCSource 32 2 1 PCWrite Control 4 PCWriteCond 2 1 x x Zero ALUOp x IorD Inst[31-26] Inst[25-0] [31-28] MemRead x x x MemWrite IRWrite MemToReg RegDest RegWrite ALUSelA PC or PC+4 x PC 1 1 [25-21] Result Zero Memory Address Write data Read data Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A [20-16] A Instr. Reg Instr. [31-0] ALU Out 1 ALUSelB x [15-11] B 1 2 3 4 MDR 1 MemRead=0 MemWrite=0 PCWrite=1 RegWrite=0 PCSource=2 sign extend Sh. Left 2 16 32 ALU control [15-0] [5-0]

14 Memory Addr. Completion
Cycle 3 LW,SW Sh. Left 2 x 26 28 Concat. PCSource 32 PCWrite Control 4 PCWriteCond 2 1 Zero ALUOp x IorD Inst[31-26] Inst[25-0] [31-28] MemRead x x MemWrite IRWrite MemToReg RegWrite ALUSelA RegDest PC or PC+4 1 PC 1 1 [25-21] Result Zero Memory Address Write data Read data Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A [20-16] A Instr. Reg Instr. [31-0] ALU Out 1 ALUSelB 2 [15-11] B 1 2 3 4 MemRead=0 MemWrite=0 IRWrite=0 ALUSelA=1 ALUSelB=2 MDR 1 ALUOp=00 PCWrite=0 PCWriteCond=0 RegWrite=0 sign extend Sh. Left 2 16 32 ALU control [15-0] [5-0]

15 Memory Read x x 1 1 x x x x Cycle 4 LW MemRead=1 MemWrite=0 IRWrite=0
Sh. Left 2 26 28 Concat. PCSource 32 x PCWrite Control 4 PCWriteCond 2 1 x Zero ALUOp 1 IorD Inst[31-26] Inst[25-0] [31-28] MemRead 1 x x MemWrite IRWrite MemToReg RegWrite ALUSelA RegDest PC or PC+4 x PC 1 1 [25-21] Result Zero Memory Address Write data Read data Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A [20-16] A Instr. Reg Instr. [31-0] ALU Out 1 ALUSelB x [15-11] B 1 2 3 4 MDR 1 MemRead=1 MemWrite=0 IRWrite=0 PCWrite=0 PCWriteCond=0 RegWrite=0 IorD=1 sign extend Sh. Left 2 16 32 ALU control [15-0] [5-0]

16 ReadWriteBack x x x x 1 1 x x Cycle 5 LW
Sh. Left 2 26 28 Concat. PCSource x 32 PCWrite Control 4 PCWriteCond 2 1 x Zero ALUOp x IorD Inst[31-26] Inst[25-0] [31-28] MemRead x 1 1 MemWrite IRWrite MemToReg RegWrite ALUSelA RegDest PC or PC+4 x PC 1 1 [25-21] Result Zero Memory Address Write data Read data Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A [20-16] A Instr. Reg Instr. [31-0] ALU Out 1 ALUSelB x [15-11] B 1 2 3 4 MemRead=0 MemWrite=0 RegDest=0 MemtoReg=1 MDR 1 PCWrite=0 PCWriteCond=0 RegWrite=1 MemToReg=1 sign extend Sh. Left 2 16 32 ALU control [15-0] [5-0]

17 Memory Write x x x x x x 1 x x Cycle 4 SW MemRead=0 MemWrite=1
Sh. Left 2 26 28 Concat. PCSource x 32 PCWrite Control 4 PCWriteCond 2 1 x Zero ALUOp x IorD Inst[31-26] Inst[25-0] [31-28] MemRead x x x 1 MemWrite IRWrite MemToReg RegWrite ALUSelA RegDest PC or PC+4 x PC 1 1 [25-21] Result Zero Memory Address Write data Read data Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A [20-16] A Instr. Reg Instr. [31-0] ALU Out 1 ALUSelB x [15-11] B 1 2 3 4 MemRead=0 MemWrite=1 MDR 1 PCWrite=0 PCWriteCond=0 RegWrite=0 sign extend Sh. Left 2 16 32 ALU control [15-0] [5-0]

18 Control Finite State Machine
ALUSelA=0 ALUSelB=11 ALUOp=0 IorD=0 MemRead=1 IRWrite=1 ALUSelA=0 ALUSelB=1 ALUOp=00 PCWrite=1 PCSource=00 Instr. Fetch t1 Instr. Decode/ Register Fetch t0 LW or SW Jump t2 ALUSelA=1 ALUSelB=2 ALUOp=0 BEQ Jump Branch Execution Mem. Addr. Completion R-type t8 t9 ALUSelA=1 ALUSelB=0 PCSource=1 ALUOp=1 PCWriteCond=1 ALUSelA=1 ALUSelB=0 ALUOp=2 PCWrite=1 PCSource=10 t6 t3 MemRead=1 IorD=1 LW Memory Access SW t7 t4 t5 RegDest=1 RegWrite=1 MemToReg=0 MemWrite=1 IorD=1 RegDest=0 RegWrite=1 MemToReg=1 Memory Access R-type Completion Write-back

19 Implementing the Control
Implementing a Finite State Machine is straightforward 10 states --> 4 flipflops Choose binary representations for each state Create state transition table Map to flipflop type Using K-maps, build a function for each control output 50-70 Gates Or..., Put the FSM into a computer program and trust it

20 Evaluation Multi-cycle goals: Reuse common parts Merge the memories
Only one ALU in the design, but more complexity Merge the memories Success! Get rid of worst-case cycle time constraint R-type: 4 cycles, Branch: 3 cycles, Jump: 3 cycles, LW: 5 cycles, SW: 4 cycles Will cycle time be 1/5 that of single cycle? No, more like 1/3 or 1/4 of the cycle time We still will win in most cases

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