1. CS 230: Computer Organization and Assembly Language
Aviral Shrivastava
Department of Computer Science and Engineering
School of Computing and Informatics
Arizona State University
Slides courtesy: Prof. Yann Hang Lee, ASU, Prof. Mary Jane Irwin, PSU, Ande Carle, UCB

2. Announcements Project 3 Midterm Finals MIPS Assembler
Thursday, Oct 2009
MIPS ISA and Programming
Function calls and register conventions
Assembling MIPS Instructions
2’s complement number system
FP number system
Finals
Tuesday, Dec 08, 2009

3. Computer Organization
software
Instruction Set Architecture
hardware
We have leaned the ISA of the processor till now
Given an algorithm, express it in terms of the processor ISA

4. Below the Program High-level language program (in C)
swap (int v[], int k)
. . .
Assembly language program (for MIPS)
swap: sll $2, $5, 2
add $2, $4, $2
lw $15, 0($2)
lw $16, 4($2)
sw $16, 0($2)
sw $15, 4($2)
jr $31
Machine (object) code (for MIPS)
C - Compiler
Assembler

5. Datapath & Control
We're ready to look at an implementation of the MIPS
Simplified to contain only:
memory-reference instructions: lw, sw
arithmetic-logical instructions: add, sub, and, or, slt
control flow instructions: beq, j
Generic implementation:
use the program counter (PC) to supply the instruction address and fetch the instruction from memory (and update the PC)
decode the instruction (and read registers)
execute the instruction
All instructions (except j) use the ALU after reading the registers
Why? memory-reference? arithmetic? control flow?
Fetch
PC = PC+4
Decode
Exec
memory reference use ALU to compute addresses
arithmetic use the ALU to do the require arithmetic
control use the ALU to compute branch conditions.

6. Abstract Implementation View
Two types of functional units:
elements that operate on data values (combinational)
elements that contain state (sequential)
Single cycle operation
Split memory (Harvard) model - one memory for instructions and one for data
Write Data
Instruction
Memory
Address
Read
Data
Register
File
Reg Addr
Data
Memory
Read Data PC
Address
Instruction
ALU
Reg Addr
Read
Data
Write Data
Reg Addr
Have the class tell which is which in the picture - combinational and sequential

7. 32-bit ALU Supports all the Arithmetic/Logic operations operation a
result 32 b 32

8. ALU Design op add/subt A0 result0 B0 A1 result1 B1 . . . zero . . .+
less A1
result1 B1 +
. . .
zero
less
For slt (and slti and sltiu and sltu)
“No integer overflow exception occurs under any circumstances. The comparison is valid even if the subtraction used during the comparison overflows.”
The way I read this is that if the result overflows during the subtraction, no attempt is made to correct the set line to reflect that!
Otherwise, you would need to add additional logic in front of the set line to do the correction in case of overflow. Like exoring the overflow bit with the sign bit.
A31
result31
overflow +
B31
less
set

9. Fetching Instructions
Fetching instructions involves
reading the instruction from the Instruction Memory
updating the PC to hold the address of the next instruction
PC is updated every cycle, so it does not need an explicit write control signal
Instruction Memory is read every cycle, so it doesn’t need an explicit read control signal
Add 4
Instruction
Memory
Read
Address PC
Instruction

10. Decoding Instructions
Decoding instructions involves
sending the fetched instruction’s opcode and function field bits to the control unit
Control
Unit
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read
Data 1
Data 2
Instruction
reading two values from the Register File
Register File addresses are contained in the instruction

11. Executing R Format Operations
R format operations (add, sub, slt, and, or)
perform the indicated (by op and funct) operation on values in rs and rt
store the result back into the Register File (into location rd)
Note that Register File is not written every cycle (e.g. sw), so we need an explicit write control signal for the Register File
R-type: 31 25 20 15 5 op rs rt rd
funct
shamt 10
RegWrite
ALU control
Read Addr 1
Read
Data 1
Register
File
Read Addr 2
overflow
Instruction
zero
ALU
Write Addr
Read
Data 2
Write Data

12. Load and Store Operations
compute a memory address by adding the base register (in rs) to the 16-bit signed offset field in the instruction
base register was read from the Register File during decode
offset value in the low order 16 bits of the instruction must be sign extended to create a 32-bit signed value
store value, read from the Register File during decode, must be written to the Data Memory
load value, read from the Data Memory, must be stored in the Register File
I-Type: op rs rt
address offset 31 25 20 15

13. Load and Store Operations
Instruction
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read
Data 1
Data 2
ALU
overflow
zero
ALU control
RegWrite
Data
Memory
Address
Read Data
Sign
Extend
MemWrite
MemRead 16 32
For lecture

14. Executing Branch Operations
Branch operations have to
compare the operands read from the Register File during decode (rs and rt values) for equality (zero ALU output)
compute the branch target address by adding the updated PC to the sign extended16-bit signed offset field in the instruction
“base register” is the updated PC
offset value in the low order 16 bits of the instruction must be sign extended to create a 32-bit signed value and then shifted left 2 bits to turn it into a word address
I-Type: op rs rt
address offset 31 25 20 15

15. Executing Branch Operations
Add
Branch
target
address
Add 4
Shift
left 2
ALU control PC
zero
(to branch control logic)
Read Addr 1
Read
Data 1
Register
File
Read Addr 2
Instruction
ALU
Write Addr
For lecture
Read
Data 2
Write Data
Sign
Extend 16 32

16. Executing Jump Operations
Jump operations have to
replace the lower 28 bits of the PC with the lower 26 bits of the fetched instruction shifted left by 2 bits 31 25
J-Type: op
jump target address
Add 4 4
Jump
address
Instruction
Memory
Shift
left 2 28
Read
Address
Instruction PC 26

17. Adding the pieces together
Read
Address
Instruction
Memory
Add PC 4
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Data 1
Data 2
ALU
ovf
zero
ALU control
RegWrite
Data
Read Data
MemWrite
MemRead
Sign
Extend 16 32

18. Multiplexor Insertion
MemtoReg
Read
Address
Instruction
Memory
Add PC 4
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Data 1
Data 2
ALU
ovf
zero
ALU control
RegWrite
Data
Read Data
MemWrite
MemRead
Sign
Extend 16 32
ALUSrc

19. Clock Distribution clock cycle System Clock MemtoReg ovf zero
Read
Address
Instruction
Memory
Add PC 4
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Data 1
Data 2
ALU
ovf
zero
ALU control
RegWrite
Data
Read Data
MemWrite
MemRead
Sign
Extend 16 32
ALUSrc

20. Adding the Branch Portion
Read
Address
Instruction
Memory
Add PC 4
Shift
left 2
Add
PCSrc
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read
Data 1
Data 2
ALU
ovf
zero
ALU control
RegWrite
Data
Memory
Address
Read Data
MemWrite
MemRead
Sign
Extend 16 32
MemtoReg
ALUSrc

21. Adding the Jump Portion32 26 1
Shift
left 2 28
PC+4[31-28]
Add
Add 4
Shift
left 2
PCSrc
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read
Data 1
Data 2
ALU
ovf
zero
ALU control
RegWrite
Data
Memory
Address
Read Data
MemWrite
MemRead
Sign
Extend 16 32
MemtoReg
ALUSrc
Instruction
Memory
Read
Address PC
Instruction

22. MIPS Machine (with Controls)
Instr[25-0] 1
Shift
left 2 28 32 26
PC+4[31-28]
Add
Add 1 4
Shift
left 2
PCSrc
Jump
ALUOp
Branch
MemRead
Instr[31-26]
Control
Unit
MemtoReg
MemWrite
ALUSrc
RegWrite
RegDst
ovf
Instr[25-21]
Read Addr 1
Instruction
Memory
Read
Data 1
Address
Register
File
Instr[20-16]
zero
Read Addr 2
For lecture
Good exam questions
Add jalr rs,rd 0 rs 0 rd 0 9
jump to instr whose addr is in rs and save addr of next inst (PC+4) in rd
Add the PowerPC addressing modes of update addressing and indexed addressing (will have to expand the RegFile to be three read port and two write port)
Add andi, ori, addi - have to have both a signextend and a zeroextend and choose between the two, will have to augment the ALUop encoding (since can’t get the op information out of the funct bits as with R-type)
Add mult rs, rt with the result being left in hi|lo - so also include the mfhi and mflo instructions (will have to add a multiplier, the hi and lo registers and then a couple of muxes and their control).
Add barrel shifter
Data
Memory
Read
Address PC
Instr[31-0]
Read Data 1
ALU
Write Addr
Read
Data 2 1
Write Data
Instr[ ]
Write Data 1
Instr[15-0]
Sign
Extend
ALU
control 16 32
Instr[5-0]

23. Yoda says…
Use your feelings, Obi-Wan, and find him you will