1. Chapter 3
Fabrication, Layout, and Simulation

2. 3.2 ic fabrication technology

3. 3.2.1 Overview of IC Fabrication Process

4. 3.2.2 IC Photolithographic Process
Patterning process

5. 3.2.2 IC Photolithographic Process
Patterning process

6. 3.2.3 Making Transistors
CMOS process
step 1 :
step 2 :
step3 :

7. 3.2.3 Making Transistors
CMOS process
step 4 :
step 5 :

8. 3.2.3 Making Transistors

9. 3.2.4 Making Wires
Wire fabrication
step 1 :
step 2 :

10. 3.2.4 Making Wires
Wire fabrication
step 3 :
step 4 :

11. 3.2.4 Making Wires

12. 3.2.5 Wire Capacitance and Resistance

13. 3.2.5 Wire Capacitance and Resistance

14. (3.1) 3.2.5 Wire Capacitance and Resistance
Parallel-plate capacitance :
Resistance :
(3.1)

15. Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.
3.2.5 Wire Capacitance and Resistance
Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.

16. 3.3 Layout basics

17. 3.3 Layout Basics

18. 3.3 Layout Basics

19. 3.3 Layout Basics

20. 3.4 Modeling the mos transistor for circuit simulation

21. 3.4.2 Specifying MOS Transistors

22. 3.4.2 Specifying MOS Transistors
SPICE effective values :
(3.2)

23. 3.5 SPIce mos level 1 device model

24. (3.3) (3.4) (3.5) (3.6) 3.5 SPICE MOS LEVEL 1 Device Model
Surface potential :
Oxide capacitance :
Body-effect parameter :
Threshold voltage :
(3.3)
(3.4)
(3.5)
(3.6)

25. (3.7) (3.8) (3.9) 3.5 SPICE MOS LEVEL 1 Device Model
Specified parameter :
Current expression
(linear region)
(saturation)
(3.7)
(3.8)
(3.9)

26. 3.5 SPICE MOS LEVEL 1 Device Model
Capacitance :
(3.10)

27. (3.11) 3.5.1 Extraction of Parameters for MOS LEVEL 1
Long-channel saturation region equation :
(3.11)

28. 3.5.1 Extraction of Parameters for MOS LEVEL 1

29. 3.6 BSIM3 model

30. 3.6 BSIM3 Model

31. 3.6 BSIM3 Model
(2.11)
(3.12)
(3.13)
(3.15)
( Threshold voltage (Sec. 2.3) : )
Threshold voltage :
Oxide capacitance :

32. 3.6 BSIM3 Model
Parameters :
Threshold voltage :
(3.14)
(3.16)
(3.17)

33. 3.6 BSIM3 Model

34. 3.6 BSIM3 Model

35. 3.6 BSIM3 Model
Threshold voltage include all side-effects:
Mobility :
Critical field :
Subthreshold current :
(3.18)
(3.19)
(3.20)
(3.21)

36. 3.6 BSIM3 Model
Capacitances :
Source/Drain resistance :
(3.22)
(3.23)

37. 3.7 Additional Effects in MOS Transistors

38. (3.24) (3.25) 3.7.2 Temperature Effects Carrier mobility :
Intrinsic carrier concentration :
(3.24)
(3.25)

39. 3.7.5 CMOS Latch-up

40. 3.8 Silicon-on-insulator (SOI) technology

41. 3.8 Silicon-on-Insulator (SOI) Technology