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Noise Analysis of CMOS Readouot Ciruits

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Presentation on theme: "Noise Analysis of CMOS Readouot Ciruits"— Presentation transcript:

1 Noise Analysis of CMOS Readouot Ciruits
“A CMOS 0.35 μm Analog Front-End Electronics for Gamma Ray Medical Imaging” suggest a noise model and analysis for circuit of analog signal processing circuit as following figure and equations. They focus on three separate contributions determine the ENC: ENCd : The input transistor channel thermal ENCf : Flicker noise ENCo : Detector leakage current and feedback resistor thermal noise These factors are depend on the circuit design. They figure out a optimum transistor width(W) which makes noise minimized with fixed drain current of CSA. Following their analysis, optimum width of input transistor is about 1 mm. Although the optimal value from the analysis minimize the noise, 1 mm is too large to be integrated. And also, we have to consider about gain and linearity of CSA. If W is increased with fixed ID (100 μA), VOV and gm would be decreased by W. Large transistor with respectively low drain current causes low gain and linearity. ENC Input Transistor Width [Meter]

2 Noise Analysis of CMOS readouot ciruits
As we mentioned above, 1mm width transistor has only 0.02 V overdrive voltage depicted on a left figure. 0.02 V of overdrive voltage is very close to threshold voltage of transistor. In the right graph, we can see the gm which is small and nonlinear. gm Gate Voltage [V] Old Value => Poor gain & linearity New Value => good gain & linearity We suggest constant overdrive voltage analysis to find out the optimum width of the transistor has small size and high linearity. Fixing the overdrive voltage to 1 V, we recalculate ENC and show on the left figure. With same noise performance, new optimum value of transistor width is much smaller size (15 μm), much higher linearity. ENC Input Transistor Width [Meter] Input Transistor Width [Meter]


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