1. ECE 3430 – Intro to Microcomputer Systems
ECE 3430 – Introduction to Microcomputer Systems University of Colorado at Colorado Springs
Lecture #4
Agenda Today
More on the “mov” instructions
Big Endian vs. Little Endian
MSP430 Addressing Modes
Lecture #4
ECE 3430 – Intro to Microcomputer Systems
Fall 2014

2. Data Movement (How It Can Be Done)
In all computer architectures, data must be moved into CPU registers for
processing (an input operation) and moved out of the registers after
processing (an output operation). The source and destination of the data
can be memory external from the CPU, I/O peripherals, or other CPU registers.
Some architectures use explicit “load” and “store” operations to move
data into and out of CPU registers. These architectures are called
load-store architectures. The MSP430, on the other hand, is not a
load/store architecture. It instead uses move instructions to accomplish
both.
All CPU architectures support a set number of addressing modes. These
addressing modes define what the operands (if any) of an instruction
represent. Recall operands provide additional information needed by
an instruction.
In the MSP430, the source and destination addressing mode is encoded in the
Instruction code—along with the opcode and register numbers.
Lecture #4
ECE 3430 – Intro to Microcomputer Systems
Fall 2014

3. Data Movement (How It Can Be Done)
The MSP430 CPU has 4 native addressing modes:
Register Direct
no operands are required, register only operations
Indexed
operand provides fixed offset applied to address held in a CPU register
Register Indirect
address is held in a CPU register – special case of indexed addressing without operand
Register Indirect Autoincrement
same as #3—but register is automatically incremented by 1 or 2
The first two can be used for both the source and destination and the second two can be used only for the source.
Lecture #4
ECE 3430 – Intro to Microcomputer Systems
Fall 2014

4. Register Direct (Addressing Mode)
mov.b R10,R11
Moves the lower byte of the contents of 16-bit CPU register R10 to CPU register R11.
mov.w R10,R12
Moves the entire 16-bit value stored in R10 to R12.
Both of these examples involve no use of the memory address or data bus (beyond reading the instruction code).
Both source and destination in this example use the register direct addressing mode.
Lecture #4
ECE 3430 – Intro to Microcomputer Systems
Fall 2014

5. Indexed (Addressing Mode)
mov.b 1(R10),4(R11)
R10 and R11 represent an address. A byte is fetched from memory location R10+1 and copied to memory location R11+4.
mov.w 2(R10),4(R12)
R10 and R12 represent an address. A word is fetched from memory location R10+2 and copied to memory location R12+4.
The fixed numbers preceding the register numbers is an operand provided outside of the 16-bit instruction code.
Lecture #4
ECE 3430 – Intro to Microcomputer Systems
Fall 2014

6. Register Indirect (Addressing Mode)
mov.b @R10,R11
Functionally the same as mov.b 0(R10),R11
Moves the byte stored at memory location represented by R10 to become the contents of R11.
mov.w @R10,R12
16-bit equivalent of the above.
Memory cycles are produced here during the instruction execution—but no operands outside of the 16-bit instruction code are required (unlike with the indexed addressing mode).
Note cannot be used for the destination. Register indirect is used for the source and register direct is used for the destination in these examples.
Lecture #4
ECE 3430 – Intro to Microcomputer Systems
Fall 2014

7. Register Indirect Autoincrement (Addressing Mode)
mov.b @R10+,R11
Moves the contents of the memory location represented by the contents of R10 into R11. After the copy operation, R10 is incremented by 1 to “point” to the next byte in memory.
mov.w @R10+,R12
16-bit equivalent of the above. After the move, the contents of R10 is incremented twice (by 2) to “point” to the next word in memory.
Note that “register indirect autoincrement” can only be used for the source and not the destination. The destination uses register direct in these examples.
Lecture #4
ECE 3430 – Intro to Microcomputer Systems
Fall 2014

8. Other Pseudo-Addressing Modes
The four native addressing modes can be used in interesting ways (along with the special behavior of the constant generators) to produce a few more useful addressing modes (the first 3 mentioned below are extensions of indexed addressing):
PC-Relative Addressing (Symbolic Addressing):
The 16-bit fixed offset (operand) applied to the PC current value. Together specifies the address of the data relative to the current PC value:
mov.w 23(PC),R10 (operand 23 is signed offset applied to PC value, word in address is copied to R10)
SP-Relative Addressing:
The 16-bit fixed offset (operand) applied to the SP current value. Together specifies the address of the data relative to the current SP value:
mov.w 0x12(SP),R12 (operand 0x12 is signed offset applied to SP value, word in address is copied to R12)
Lecture #4
ECE 3430 – Intro to Microcomputer Systems
Fall 2014

9. Other Pseudo-Addressing Modes
Absolute Addressing (SR-Relative):
The 16-bit operand is the absolute address:
mov.w 0x1234(SR), R11 (word at memory location 0x1234 copied to R11, SR reads as 0)
Immediate Addressing:
The operand immediately following the instruction code is the raw data to initialize a register or memory location to:
mov.w @PC+,R12 (next 16-bit value in memory represents data to load into R12)
(see MSP430 Instruction Set Encodings link on course web page)
Lecture #4
ECE 3430 – Intro to Microcomputer Systems
Fall 2014

10. Other Pseudo-Addressing Modes
The assembler will allow use of these pseudo-addressing modes using special notation. It will convert them into the appropriate native addressing mode for you.
PC-Relative (Symbolic) Addressing:
mov.w myVar, R6  mov.w x(PC),R6
Where x represents the number of bytes away the variable lives from where you are.
Use symbolic variable names without a prefix.
Typically use for RAM variables.
Absolute Addressing:
mov.b &P1IN,R6  mov.b P1IN(SR),R6
The absolute address of register “P1IN” is substituted in by assembler.
Use ‘&’ symbol in front of variable names to specify the use of this addressing mode.
Use for I/O in the lab. Typically this addressing mode is used to interact with on-chip peripheral devices.
Immediate Addressing:
mov.w #1234,R7  mov.w @PC+,R7
The immediate value 1234 is stored in the two bytes of memory immediately following the instruction code.
Use the # sign in front of a number to specify the use of this addressing mode.
Lecture #4
ECE 3430 – Intro to Microcomputer Systems
Fall 2014

11. Big Endian vs. Little Endian
Suppose I wanted to do two 16-bit loads from memory locations 0x0000 and 0x0002…
Big Endian (Motorola/Freescale Architectures, …):
After a 16-bit load from 0x0000, I would see in CPU registers: 0x1234
After a 16-bit load from 0x0002, I would see in CPU registers: 0x5678
Little Endian (Intel Architectures and MSP430 and others):
After a 16-bit load from 0x0000, I would see in CPU registers: 0x3412
After a 16-bit load from 0x0002, I would see in CPU registers: 0x7856
Endian-ness applies to all memory accesses greater than 8-bits (i.e. 16-bit, 32-bit, 64-bit, 128-bit)
Generally speaking, higher-level programmers are insulated from these architectural differences.
M(0000h)=12h
M(0001h)=34h
M(0002h)=56h
M(0003h)=78h
Lecture #4
ECE 3430 – Intro to Microcomputer Systems
Fall 2014

12. ECE 3430 – Intro to Microcomputer Systems
Further Explanation
Immediate Addressing – The operand of the instruction is the “actual data” to be loaded into a register or memory location.
The “#” sign indicates to the cross-assembler that
“immediate addressing” is intended.
Ex) mov.w #0xABCD,R ; this instruction will put 0xABCD into register R5
mov.b # b,R ; this instruction will put b into register R6
Mnemonics
Machine code: 0x???? 0xABCD
Operands
Memory
0x0000 0x??
0x0001 0x??
0x0002 0xCD
0x xAB
Unique code to MSP430, the control unit in the CPU decodes instruction codes and knows what to do (i.e. put 0xABCD into R5 or put 0xAF into R6)
How it looks in memory
Lecture #4
ECE 3430 – Intro to Microcomputer Systems
Fall 2014

13. Further Explanation
Indexed Addressing – The contents of registers are added to the operand of the instruction to form the effective address.
The operand acts as an “offset” from where R? is
pointing in memory. The R? registers need to be initialized.
Ex) mov.w #0x0100,R5 ; initializes the R5 register to 0x0100 using immediate addressing mov.w 2(R5),R ; loads register R6 with the contents of memory location 0x0102
; and 0x0103:
Mnemonics
Machine code: 0x???? 0x02
Memory
0x0000 0x??
0x0001 0x??
0x0002 0x02
0x0003 0x00
0x0101 -
0x0102 0x56
0x0103 0x78
R6 = 0x7856 after this instruction is executed
The control unit knows that 0x???? means mov.w 2(R5),R6
Lecture #4
ECE 3430 – Intro to Microcomputer Systems
Fall 2014

14. Further Explanation
Relative Addressing – Be it PC-relative or SP-relative, this is the same as
indexed. Note: SR-relative is absolute since the SR
acts as a 0 constant generator in that case.
The offset is a 16-bit signed offset. This means the “effective
address” can be anything in the 16-bit address space!
Ex) mov.w 0xFF00(SR),R8 ; This will copy M(0xFF00) to R8
Machine code: 0x???? 0xFF00
Memory
Opcode Operand
0x0000 0x??
0x0001 0x??
0x0002 0x00
0x0003 0xFF
0xFF00 0x12
0xFF01 0x34
0xFF02 0x56
R8 = 0x3412 after the instruction is executed.
NOTE: The source and destination address of a 16-bit move must be even. Hence, replacing 0xFF00 with 0xFF01 would lead to unpredictable behavior!
Lecture #4
ECE 3430 – Intro to Microcomputer Systems
Fall 2014

15. ECE 3430 – Intro to Microcomputer Systems
Final Notes
The program counter (PC/R0) and status register (SR/R2/CG1) are
not explicitly loaded with move instructions!
The PC is initialized via reset interrupt vectors (discussed later)
and the status register is modified automatically by the ALU as a result
of instruction execution.
The stack pointer (SP/R1) is initialized by software during execution
(discussed later). It is not required that it be initialized if the system
generates no interrupts and makes no use of subroutines (all discussed later).
R3/CG2 should never be loaded. It should only be used as a source for
instructions.
Lecture #4
ECE 3430 – Intro to Microcomputer Systems
Fall 2014

16. ECE 3430 – Intro to Microcomputer Systems
Final Notes
Only use R4-R15 for general-purpose use.
When referring to PC, SP, or SR, you may need to refer to them using their
true register names. Some assemblers may not know what they mean. Same
thing with CG1 and CG2.
Lecture #4
ECE 3430 – Intro to Microcomputer Systems
Fall 2014

17. To Find Out More About MSP430 Instructions
See the chapter 5 (section 4) of the text book (don’t worry about instructions we have not covered).
See the MSP430 Instruction Set Summary and Instruction Set encodings links on the course web page.
You will need to reference this when doing homework #2.
Lecture #4
ECE 3430 – Intro to Microcomputer Systems
Fall 2014