1. LATCHED, FLIP-FLOPS,AND TIMERS

2. INTRODUCTION
Latches and flip-flops are the basic single-bit memory elements used to build sequential circuit with one or two inputs/outputs, designed using individual logic gates and feedback loops.
Latches:
The output of a latch depends on its current inputs and on its previous output and its change of state can happen at any time when its inputs change.
Flip-Flops:
The output of a flip-flop also depends on current inputs and its previous output but the change of state occurs at specific times determined by a clock input.

3. INTRODUCTION
Latches:
S-R Latch
Gate S-R Latch
Gate D-Latch
Flip-Flops:
Edge-Triggered Flip-Flop (S-R, J-K, D)
Asynchronous Inputs
Master-Slave Flip-Flop
Flip-Flop Operating Characteristics
Flip-Flop Applications
One-shots & The 555 Timer

4. An Active High Input S-R (Set – Reset) Latch

5. An Active Low Input (Set – Reset) Latch

6. EXAMPLE
If the waveform in figure below are applied to the inputs of the active LOW input latch, determine the waveform that will be observed on the Q output. Assume that Q is initially LOW.

7. The Gated S-R (Set – Reset) Latch
A gate input is added to the S-R latch to make the latch synchronous.
A gated latches requires input, EN.
In order for the set and reset inputs to change the latch, the gate input must be active (high/Enable).
When the gate input is low, the latch remains in the hold condition.

8. Example: The Gated S-R (Set – Reset) Latch
Determine the Q output waveform if the inputs in figure below are applied to a gated D latch, which is initially RESET

9. The Gated D Latch
The D (data) latch has a single input that is used to set and to reset the flip-flop.
When the gate is high, the Q output will follow the D input.
When the gate is low, the Q output will hold.

10. The Gated D Latch (74LS75)

11. EXAMPLE
Determine the Q output waveform if the inputs shown in figure below are applied to a gated D latch, which is initially RESET

12. Edge Triggered Flip-Flops
An edge triggered flip-flop changes state either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock pulse and is sensitive to its inputs only at this transition of the clock.
Can be either positive edge triggered (no bubble at C input) or negative edge triggered (bubble at C input).

13. Clock Signals & Synchronous Sequential Circuits
Rising edges of the clock
(Positive-edge triggered)
Falling edges
of the clock
(Negative-edge triggered)
Clock signal
Clock Cycle
Time 1
A clock signal is a periodic square wave that indefinitely switches values from 0 to 1 and 1 to 0 at fixed intervals.

14. Operation of a positive edge-triggered S-R flip-flop
The S and R inputs of the S-R flip flop are called synchronous input because data on these inputs are transferred to the flip flop’s output only on the triggering edge of the clock pulse.

15. Truth Table for a positive edge-triggered S-R flip-flop

16. EXAMPLE
Determine the output waveforms of the flip-flops in figure below for S,R, and CLK inputs. Assume that the positive edge triggered flip flops is initially RESET.

17. A positive edge-triggered D flip-flop formed with an S-R flip-flop and an inverter

18. EXAMPLE
Given the waveforms in figure below for the D input and the clock, determine the Q output waveform if the flip flops starts out RESET.

19. Edge-Triggered J-K flip-flop

20. Edge-triggered J-K flip-flop
The edge-triggered J-K will only accept the J and K inputs during the active edge of the clock.
The small triangle on the clock input indicates that the device is edge-triggered.
A bubble on the clock input indicates that the device responds to the negative edge. no bubble would indicate a positive edge-triggered device.

21. Transitions illustrating the toggle operation when J =1 and K = 1

22. EXAMPLE (Positive Edge Triggered)
The waveform in figure below are applied to the flip flop as shown. Determine the Q output, starting in the RESET state.

23. EXAMPLE (Negative Edge Triggered)
The waveforms in figure below are applied to the J,K, and clock inputs as indicated. Determine the Q output, assuming that the flip flop is initially RESET.

24. Logic symbol for a J-K flip-flop with active-LOW preset and clear inputs.
An active level on the preset input will set the flip flop, and an active level on the clear input will reset it.
These input affect the state of the flip flop independent of the clock.

25. Logic diagram for a basic J-K flip flop with active LOW preset and clear inputs

26. EXAMPLE
For the positive edge triggered J-K flip flop with preset and clear inputs in figure below, determine the output Q for the input shown in the timing diagram if Q is initially LOW.

27. Flip-flops used in a basic register for parallel data storage

28. Frequency Division (J-K flip-flop as a divide-by-2 device
Frequency Division (J-K flip-flop as a divide-by-2 device. Q is one-half the frequency of CLK)

29. Two J-K flip-flops used to divide the clock frequency by 4
Two J-K flip-flops used to divide the clock frequency by 4. QA is one-half and QB is one-fourth the frequency of CLK.

30. EXAMPLE
Develop the fout waveform for circuit in figure below when an 8kH square wave input is applied to the clock input of the flip flop A.

31. Flip-flops used to generate a binary count sequence
Flip-flops used to generate a binary count sequence. Two repetitions (00, 01, 10, 11) are shown

32. EXAMPLE
Determine the output waveforms in relation to the clock for QA, QB and QC in the circuit of figure below and show the binary sequence represented by these waveform.

33. Basic operation of a 555 Timer
Threshold
Control Voltage
Trigger
Discharge
Reset
Output

34. Functional Diagram of 555 Timer
Monostable (one-shot) operation
Astable operation

35. Monostable (one-shot) operation
tw=1.1R1C1

36. Monostable (one-shot) operation