1. Digital Electronics Multiplexer

2. Mux Based Design
Implements a 4-input active low majority function using a 8:1 multiplexer. The four inputs are A, B, C and D. A 4-input active low majority function outputs a logic 0 if any three out of its four inputs are 0’s; otherwise, it outputs a one. Y
I0 I1 I2 I3 I4 I5 I6 I7 S2
8:1 MUX S1 S0

3. Mux Based Design Solution
A B C D Y D 1 Y
I0 I1 I2 I3 I4 I5 I6 I7 S2
8:1 MUX S1 S0
A B C

4. Programmable Devices (Actel)
Implement the following functions using the a basic Actel logic module.
A + B
A + B + C
A’ + B’ + C’
A + B + C + D
AB + BC + AC

5. Programmable Devices (Actel) Solution (#1/6)
I0 I1 I2 I3
C1 C0
4:1 mux Z Z
I0 I1 C1 C0
2:1 mux
4:1 mux
I2 I3
Modified 4:1 multiplexer
Lower Bound: Any function of 3 variables can
be implemented
Additional OR gate and separate SOA and S0B
enables implementation of functions with more
than 3 variables

6. Programmable Devices (Actel) Solution (#2/6)
2:1 MUX
D0 = X
D1 = X
SOA = X
D2 = B
D3 = 1
SOB = A
S0= 1 Y
S1 = X
A + B
A B Y
0 0 0
0 1 1
1 0 1
1 1 1

7. Programmable Devices (Actel) Solution (#3/6)
A + B + C
SOA = B
S0= A
S1 = 0
D0 = C
2:1 MUX
D1 = 1
2:1 MUX Y
ABC Y
000 0
001 1
010 1
011 1
100 1
101 1
110 1
111 1
A + B + C
D2 = 1
2:1 MUX
D3 = 1
SOB = B

8. Programmable Devices (Actel) Solution (#4/6)
A’ + B’ + C’
SOA = B
S0= A
S1 =0
D0 = 1
ABC Y
000 1
001 1
010 1
011 1
100 1
101 1
110 1
111 0
2:1 MUX
D1 = 1
A’ + B’ + C’
2:1 MUX Y
D2 = 1
2:1 MUX
D3 = C’
SOB = B

9. Programmable Devices (Actel) Solution (#5/6)
A + B + C + D
2:1 MUX
D0 = C
D1 = 1
SOA = B
D2 = 1
D3 = 1
SOB = B
S0= A Y
S1 = D
A + B + C + D F
A + D + B + C
F = A + D
FBC Y
000 0
001 1
010 1
011 1
100 1
101 1
110 1
111 1

10. Programmable Devices (Actel) Solution (#6/6)
AB + BC + AC
2:1 MUX
D0 = 0
D1 = C
SOA = B
D2 = C
D3 = 1
SOB = B
S0= A Y
S1 = 0
AB + BC + AC
ABC Y
000 0
001 0
010 0
011 1
100 0
101 1
110 1
111 1

11. Programmable Devices (Actel)
Implement half and full adders using the a basic Actel logic module.

12. Programmable Devices (Actel) Solution (#1/2)
SUM = A’B + AB’ CO = AB
Half Adder
2:1 MUX
D0 = X
D1 = X
SOA = X
D2 = 0
D3 = B
SOB = A
S0= 1 Y
S1 = X AB CO
2:1 MUX
D0 = X
D1 = X
SOA = X
D2 = B
D3 = B’
SOB = A
S0= 1 Y
S1 = X
A’B + AB’
SUM
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

13. Programmable Devices (Actel) Solution (#2/2)
Full Adder
SUM = ABCin + A’B’Cin + A’BCin’ + AB’Cin’
CO = AB + AC + BC
2:1 MUX
D0 = Cin
D1 = Cin’
SOA = B
D2 = Cin’
D3 = Cin
SOB = B
S0= A Y
S1 = 0
SUM
2:1 MUX
D0 = 0
D1 = Cin
SOA = B
D2 = Cin
D3 = 1
SOB = B
S0= A Y
S1 = 0 CO

14. Programmable Devices (Xilinx)
The Xilinx CLB can implement any single combinational logic function F(A, B, C, D, E), OR two independent functions F(A, B, C, D), and G(A, B, C, D) of four (or less) variables.
Show how this might be implemented by wiring up a 32-bit function generator (multiplexer/selector) using two 16-to-1 and three 2-to-1 multiplexers.
Besides the five data inputs A, B, C, D, and E, there is a control input M such that when M = 0 the function generator generates the two independent 4-variable functions F and G, and when M = 1 it generates the single 5-variable function on both the F and G outputs.
What must the input settings be to implement the 5-variable function F = A xor B xor C xor D xor E?
What must the input setting be to implement the two 3-variable functions function F = A xor B xor C (full adder sum) and G = A B + BC + AC (full adder sum)?

15. Programmable Devices Solution (#1/3) (Xilinx)
The Xilinx CLB
2 FFs
Any function of
5 Variables
Global Reset
Clock, Clock Enb
Independent DIN

16. Programmable Devices Solution (#2/3) (Xilinx)
The Xilinx Function Generator
Any function of 5 variables
Two Independent Functions
of 4 variables each

17. Programmable Devices Solution (#3/3) (Xilinx)
16:1
Mux E 15
A B C D 16 31 M F G

18. Barrel Shifter S1 S0 O3 O2 O1 O0 0 0 I3 I2 I1 I0 0 1 I0 I3 I2 I1
Barrel Shifter
A barrel shifter is circuit that allows its input to be shifted any number of positions. For example, a 4-bit rotating barrel shifter can shift its inputs I3, I2, I1, I0, zero, one, two, or three positions to the right as indicated by the shift control inputs S1, S0. The outputs become:
(a)    Using conventional multiplexers, decoders, and logic gates, show how to implement the barrel shifter as a purely combinational logic circuit.
(b)    Take a different approach by implementing the barrel shifter as a Finite State Machine plus simple datapath. Define the control signals between your controller and datapath, and show your detailed state machine for implementing the correct behavior of the barrel shifter as indicated above.
(c)    Compare and contrast your answers to (a) and (b). Which is faster? Which utilizes more hardware? Which is the better design and under what circumstances?
S1 S0 O3 O2 O1 O0
I3 I2 I1 I0
I0 I3 I2 I1
I1 I0 I3 I2
I2 I1 I0 I3

19. Barrel Shifter Solution (1/4)
Barrel Shifter Solution (1/4)
(a)    Using conventional multiplexers, decoders, and logic gates, show how to implement the barrel shifter as a purely combinational logic circuit.

20. Barrel Shifter Solution (2/4)
Barrel Shifter Solution (2/4)
(b)  Take a different approach by implementing the barrel shifter as a Finite State Machine plus simple datapath. Define the control signals between your controller and datapath, and show your detailed state machine for implementing the correct behavior of the barrel shifter as indicated above.
Assumptions:
(1) User needs to press the load button to start the shift after the input.
(2) Before the next input, user has to wait at least 4 clock cycles.
States: Start  initialize the FSM
Shift  the shift register is performing shifting
Inputs: Load  User presses the load button to start the shifter
Ready  signal from datapath to indicate if the output is ready
Outputs: Shift  Keep shifting at each clock cycle until the output is ready

21. Barrel Shifter Solution (3/4)
Barrel Shifter Solution (3/4)
(b)  Take a different approach by implementing the barrel shifter as a Finite State Machine plus simple datapath. Define the control signals between your controller and datapath, and show your detailed state machine for implementing the correct behavior of the barrel shifter as indicated above.
CLK
load 2 -
bit counter
S[1:0]
bit comparator
ready
SLI O3
I[3:0] R L CE
Shift 4
bit shift register
O[3:0]
Reset
Start
Ready / shift

22. Barrel Shifter Solution (4/4)
Barrel Shifter Solution (4/4)
(c)    Compare and contrast your answers to (a) and (b). Which is faster? Which utilizes more hardware? Which is the better design and under what circumstances?
(a) is faster since the time delay for the 4:1 mux is far less than that for the shift register.
(b) uses more hardware.
If space and response time are the critical considerations, (a) yields the best design.