1. Clock & Data Recovery
Performance testing use MATLAB

2. Outline CDR Architecture & simulation flow Noise Jitter Model
CDR Jitter tolerance & Performance limited
Furture Work

3. CDR Architetcure Mapping RTL-Verilog to Matlab code.
Verify with “Verilog model test pattern” .

4. Simulation Flow
Simulation Flow

5. Noise Jitter Model USB2.0 specification:EYE pattern
“Universal Serial Bus Specification” page.131

6. Noise Jitter Model USB2.0 specification:EYE pattern
“Universal Serial Bus Specification” page.134

7. Noise Jitter Model
Jitter Model

8. Noise Jitter Model Sinusoildal Jitter modulation
[1] J. Kim, D-K. Jeong, “Multi-Gigabit-Rate Clock and Data Recovery Based on Blind Oversampling,” IEEE Communications Mag., Dec. 2003, pp.68-74
[2] Jitter generation and measurement with off-the-shelf test equipment . Slobodan Milijevic, Zarlink Semiconductor
[3] B. J. Lee, M.S. Hwang, J. Kim, DK. Jeong“A Quad 3.125Gbps Transceiver Cell with All-Digital Data Recovery Circuits,”IEEE Symposium on VLSI Circuits Digest of Technical Papers, pp , 2005

9. Noise Jitter Model
Jitter add

10. Noise Jitter Model Sinusoildal Jitter modulation Matlab simulation
with sin Jitter Offset=0.15UI , Jitter Frequency=60MHz
Unjittered Data
Jittered Data
Sin Jitter source

11. Noise Jitter Model EYE pattern with Jitter-add
Matlab simulation EYE pattern
with Jitter Offset=0.15UI , Jitter Frequency=6MHz
Unjittered Data
Jittered Data
USB20 spec.
EYE pattern(0.15UI)

12. CDR Jitter tolerance Simulation Result
Jitter Offset=0.27UI , Jitter Frequency=24MHz

13. CDR Jitter tolerance
Weight
Modification

14. CDR Jitter tolerance
Simulation Result
W: Windows Size

15. Furture Work Make Jitter Model more accurate.
Tune CDR Low Frquency & High Frequecny jitter-tolerance
Performance & Area cost trade-off.