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4.VHDL/Verilog Hierarchical Description

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1 4.VHDL/Verilog Hierarchical Description

2 Hierarchical Connections: What port directions can be connected?
Case Study: Upper level to lower level or vice versa Input to input: ALLOWED Input to output or output to input: NOT ALLOWED Input is already driven from outside. Don’t try to drive it from inside! Output to output: ALLOWED The output has to be driven from inside Bidirectional: Only to Bidirectional Top_module Module1 Din Din Dout 8 A 8 8 B EN EN CLK A Module2 Data Din Data 8 8 8 C EN CLK CLK

3 Hierarchical Connections: What port directions can be connected?
Case Study: At the same level Input to input: Allowed, but the connecting signal has to be driven! i.e. also connected to a source (output) Input to output or output to input: ALLOWED Output to output: Not ALLOWED Do not try to drive a signal by two different circuits! Bidirectional: Only to Bidirectional Top_module Module1 Din Din Dout 8 A 8 8 B EN EN CLK A Module2 Data Din Data 8 8 8 C EN CLK CLK

4 Hierarchical Connections: Code example
SSG Decoder: module Ssg_decoder #( parameter CLK_FREQ = , parameter REFRESH_RATE = 1000 ) ( input CLK, input RESET, input [15:0] DIN, output [3:0] AN, output [6:0] SSG ); //We have to define the internal signals wire CE; wire [3:0] AN_Int; wire [1:0] mux_addr; wire [3:0] mux_data; #(CLK_FREQ, REFRESH_RATE) #(CLK_FREQ REFRESH_RATE) Ssg_decoder Ssg_decoder Freq_divider CLK CLK #(CLK_FREQ, DIV_RATE) CLK CE_div CE CE Shift_reg_walk_0 AN 4 AN CLK RESET RESET AN AN_Int RESET 4 4 CE AN_Int Priority_decoder Din Dout 4 mux_addr 2 mux_addr Din[3:0] 2 I0 Mux_4X_4To1 4 Din 16 Din [7:4] I1 mux_data mux_data 4 O Hex_to_ssg_encoder I2 7 SSG SSG 16 4 [11:8] 4 Din Dout A I3 4 7 7 [15:11] 4

5 Hierarchical Connections: Code example
SSG Decoder: //connect now the internal modules //each module connection can be taken //from its definition: #(CLK_FREQ REFRESH_RATE) #(CLK_FREQ REFRESH_RATE) Ssg_decoder Ssg_decoder Freq_divider CLK CLK #(CLK_FREQ, DIV_RATE) CLK CE_div CE module #( parameter ) ( input output ); #( ) ( ); . CE Freq_divider CLK_FREQ DIV_RATE CLK, CE_div Shift_reg_walk_0 AN 4 AN CLK = , = 50000 RESET RESET AN AN_Int RESET 4 4 CE AN_Int Priority_decoder Din Dout 4 mux_addr 2 mux_addr Din[3:0] 2 I0 Mux_4X_4To1 [7:4] 4 Din 16 Din I1 mux_data mux_data 4 O Hex_to_ssg_encoder I2 7 SSG SSG 16 4 4 [11:8] Din Dout A I3 7 4 7 [15:11] 4

6 Hierarchical Connections: Code example
SSG Decoder: //connect now the internal modules //each module connection can be taken //from its definition: #(CLK_FREQ REFRESH_RATE) #(CLK_FREQ REFRESH_RATE) #(CLK_FREQ REFRESH_RATE) Ssg_decoder Ssg_decoder Freq_divider CLK CLK #(CLK_FREQ, DIV_RATE) #(CLK_FREQ, DIV_RATE) CLK CE_div Freq_divider #( . CLK_FREQ . DIV_RATE ) ( . CLK . CE_div ); (CLK_FREQ), (REFRESH_RATE) My_Freq_divider_inst (CLK), (CE) CE CE Shift_reg_walk_0 AN 4 AN CLK RESET RESET AN AN_Int RESET 4 4 CE AN_Int Priority_decoder Din Dout 4 mux_addr 2 mux_addr Din[3:0] 2 I0 Mux_4X_4To1 Remember: If the module has parameters to override, the instance name comes AFTER the parameter connections! Check for the commas in the parameter and port list! Din 16 Din [7:4] 4 I1 mux_data mux_data 4 O Hex_to_ssg_encoder I2 7 SSG SSG 16 [11:8] 4 4 Din Dout A I3 7 4 7 [15:11] 4

7 Hierarchical Connections: Code example
SSG Decoder: #(CLK_FREQ REFRESH_RATE) #(CLK_FREQ REFRESH_RATE) #(CLK_FREQ REFRESH_RATE) Ssg_decoder Ssg_decoder Freq_divider #( . CLK_FREQ (CLK_FREQ), . DIV_RATE (REFRESH_RATE) ) My_Freq_divider_inst ( . CLK (CLK) . CE_div (CE) ); //OR, keeping the order of parameters and //ports, the shortened version does not have //to contain the formal (internal) //parameters and ports: Freq_divider #(CLK_FREQ, REFRESH_RATE) My_Freq_divider_inst (CLK, CE); Freq_divider CLK CLK #(CLK_FREQ, DIV_RATE) #(CLK_FREQ, DIV_RATE) CLK CE_div CE CE Shift_reg_walk_0 AN 4 AN CLK RESET RESET AN AN_Int RESET 4 4 CE AN_Int Priority_decoder Din Dout 4 mux_addr 2 mux_addr Din[3:0] 2 I0 Mux_4X_4To1 Din 16 Din [7:4] 4 I1 mux_data mux_data 4 O Hex_to_ssg_encoder I2 7 SSG SSG 16 4 4 //NOT RECOMMENDED FOR //LARGE COMPONENTS: REDUCES //CODE VISIBILITY DRASTICALLY [11:8] Din Dout A I3 7 4 7 [15:11] 4

8 Hierarchical Connections: Code example
SSG Decoder: //In a similar manner: Shift_reg_walk_0 My_shift_reg_inst (.CLK (CLK), .RESET (RESET), .CE (CE), .AN (AN_Int) ); Priority_decoder My_decoder (.Din (AN_Int), .Dout (mux_addr)); Mux_4X_To1 My_mux_inst (.I0 (Din[3:0]), .I1 (Din[7:4]), .I2 (Din[11:8]) .I3 (Din[15:11]), .A (mux_data), .O (mux_addr) ); Hex_to_ssg_encoder My_encoder_inst (.Din (mux_data), .Dout (SSG) ); endmodule SSG Decoder: //In a similar manner: Shift_reg_walk_0 My_shift_reg_inst (.CLK (CLK), .RESET (RESET), .CE (CE), .AN (AN_Int) ); Priority_decoder My_decoder (.Din (AN_Int), .Dout (mux_addr)); Mux_4X_To1 My_mux_inst (.I0 (Din[3:0]), .I1 (Din[7:4]), .I2 (Din[11:8]), .I3 (Din[15:11]), .A (mux_data), .O (mux_addr) ); Hex_to_ssg_encoder My_encoder_inst (.Din (mux_data), .Dout (SSG) ); endmodule #(CLK_FREQ REFRESH_RATE) #(CLK_FREQ REFRESH_RATE) #(CLK_FREQ REFRESH_RATE) Ssg_decoder Ssg_decoder Freq_divider CLK CLK #(CLK_FREQ, DIV_RATE) #(CLK_FREQ, DIV_RATE) CLK CE_div CE CE Shift_reg_walk_0 AN 4 AN CLK RESET RESET AN AN_Int RESET 4 4 CE AN_Int Priority_decoder There are at least two errors in the code! Where? Din Dout 4 mux_addr 2 mux_addr Din[3:0] 2 I0 Mux_4X_4To1 [7:4] 4 Din 16 Din I1 mux_data mux_data 4 O Hex_to_ssg_encoder I2 7 SSG SSG 16 4 4 [11:8] Din Dout A I3 7 4 7 [15:11] 4

9 Hierarchical Connections: Code example
SSG Decoder: //Corrected version: Shift_reg_walk_0 My_shift_reg_inst (.CLK (CLK), .RESET (RESET), .CE (CE), .AN (AN_Int) ); Priority_decoder My_decoder (.Din (AN_Int), .Dout (mux_addr)); Mux_4X_To1 My_mux_inst (.I0 (Din[3:0]), .I1 (Din[7:4]), .I2 (Din[11:8]), .I3 (Din[15:11]), .A (mux_addr), .O (mux_data) ); Hex_to_ssg_encoder My_encoder_inst (.Din (mux_data), .Dout (SSG) ); endmodule #(CLK_FREQ REFRESH_RATE) #(CLK_FREQ REFRESH_RATE) #(CLK_FREQ REFRESH_RATE) Ssg_decoder Ssg_decoder Freq_divider CLK CLK #(CLK_FREQ, DIV_RATE) #(CLK_FREQ, DIV_RATE) CLK CE_div CE CE Shift_reg_walk_0 AN 4 AN CLK RESET RESET AN AN_Int RESET 4 4 CE AN_Int Priority_decoder Din Dout 4 mux_addr 2 mux_addr Din[3:0] 2 I0 Mux_4X_4To1 4 Din 16 Din [7:4] I1 mux_data mux_data 4 O Hex_to_ssg_encoder I2 7 SSG SSG 16 4 4 [11:8] Din Dout A I3 7 4 7 [15:11] 4

10 Hierarchical Connections Example in VHDL
SSG Decoder: architecture my_arch of ssg_decoder is --internal signals signal CE: std_logic; signal AN_Int: std_logic_vector (3 downto 0); signal mux_addr: std_logic_vector (1 downto 0); signal mux_data: std_logic_vector (3 downto 0); --we have to declare each component --if not included in library component Freq_divider generic ( CLK_FREQ: integer := ; DIV_RATE : integer := 1000 ); port (CLK : in std_logic; CE_div: out std_logic ) end component; … begin CLK CE_div Freq_divider Din 16 Ssg_decoder CE Shift_reg_walk_0 RESET AN 4 Dout Priority_decoder 2 I0 I1 I2 I3 O A Mux_4X_4To1 Hex_to_ssg_encoder 7 SSG Din[3:0] [7:4] [11:8] [15:11] AN_Int mux_data mux_addr #(CLK_FREQ REFRESH_RATE) #(CLK_FREQ, DIV_RATE) For component declaration the semicolon is present Every signal and component declaration is done between the architecture… begin statements

11 Hierarchical Connections Example in VHDL
SSG Decoder: … begin My_Freq_divider_inst: Freq_divider generic map ( CLK_FREQ => CLK_FREQ, DIV_RATE => REFRESH_RATE ) port map CLK => CLK, CE_div => CE ); -- other instantiations -- and statements end architecture my_arch; CLK CE_div Freq_divider Din 16 Ssg_decoder CE Shift_reg_walk_0 RESET AN 4 Dout Priority_decoder 2 I0 I1 I2 I3 O A Mux_4X_4To1 Hex_to_ssg_encoder 7 SSG Din[3:0] [7:4] [11:8] [15:11] AN_Int mux_data mux_addr #(CLK_FREQ REFRESH_RATE) #(CLK_FREQ, DIV_RATE) Component instantiations and statements are done between the begin… end architecture statements For component instantiation the semicolon is not present Generic map and port map statements are followed by a list of ports, separated by commas

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