1. Lecture L5.1 Mealy and Moore Machines
Finite State Machines
Lecture L5.1
Mealy and Moore Machines

2. Canonical Sequential Network
State Register
Combinational
Network
x(t)
s(t+1)
s(t)
z(t)
clk
init
present
state
input
next
output

3. Mealy Machine init s(t+1) State Register C1 next C2 s(t) present z(t)
clk
init
present
state
input
next C2

4. Moore Machine init C2 z(t) s(t+1) State Register C1 next s(t) present
clk
init
present
state
input
next C2

5. VHDL Canonical Sequential Network
init
Combinational
Network
s(t+1)
s(t)
State Register
next
state
present
state
x(t)
present
input
process(clk, init)
present
output
clk
z(t)
process(present_state, x)

6. VHDL Mealy Machine process(present_state, x) init s(t+1)
State Register
next
state
s(t)
present
state
z(t)
x(t)
present
input
process(present_state, x)
clk
process(clk, init)

7. VHDL Moore Machine init C2 z(t) s(t+1) State Register C1 next s(t)
present
state
x(t)
present
input
process(present_state, x)
process(present_state)
clk
process(clk, init)

8. Example Detect input sequence 1101
din
fsm
clk
dout
clr
din
dout

9. Easy Solution: Use Shift Register
dout 1 1 1
din Q0 Q1 Q2 Q3 D Q D Q D Q D Q
CLK !Q
CLK !Q
CLK !Q
CLK !Q
CLK

10. More General: Use State Diagram Detect input sequence 1101S1 1 1 S0
S11
CLR 1 1
S1101 1
S110 1

11. fsm.vhd
din
fsm
clk
dout
clr

12. fsm.vhd

13. fsm.vhd

14. fsm.vhd S0 S1
S11
S110
S1101 1
CLR

15. fsm.vhd S0 S1
S11
S110
S1101 1
CLR

16. fsm.vhd

17. fsmx.vhd fsmx LD1 din fsm SW1 dout clr LD8 bn IBUFG clk BTN4 clk_pulse
mclk
clkdiv

18. clk_pulse entity cclk clr BTN4 clk_pulse clk entity clk_pulse is
port (
BTN4, cclk, clr: in std_logic;
clk: out std_logic );
end clk_pulse;
cclk
clr
BTN4
clk_pulse
clk

19. clk_pulse
cclk
BTN4
delay1
delay3
delay2
clk

20. cclk
BTN4
delay1
delay3
delay2
clk
BTN4
clk

21. clk_pulse architecture
architecture clk_pulse_arch of clk_pulse is
signal delay1, delay2, delay3: std_logic;
begin
process(clk, clr)
if clr = '1' then
delay1 <= '0';
delay2 <= '0';
delay3 <= '0';
elsif clk'event and clk='1' then
delay1 <= BTN4;
delay2 <= delay1;
delay3 <= delay2;
end if;
end process;
clk <= delay1 and delay2 and (not delay3);
end clk_pulse_arch ;

22. fsmx.vhd entity fsmx is port( mclk : in STD_LOGIC; bn : in STD_LOGIC;
SW1 : in STD_LOGIC;
BTN4 : in STD_LOGIC;
led: out std_logic;
ldg : out STD_LOGIC;
LD : out STD_LOGIC_VECTOR(1 to 2) );
end fsmx;

23. fsmx.vhd

24. fsmx.vhd component clk_pulse port( BTN4 : in std_logic;
cclk : in std_logic;
clr : in std_logic;
clk : out std_logic);
end component;
signal clr, clk, cclk, bnbuf: std_logic;
signal clkdiv: std_logic_vector(23 downto 0);

25. fsmx.vhd U0: clk_pulse port map
(BTN4 => BTN4, cclk => cclk, clr =>clr, clk => clk);
U1: fsm port map
(clr =>clr, clk => clk, din => SW1, dout => LD(2));
LD(1) <= SW1;

26. Detect input sequence 1101

27. fsmv.v Verilog // Finite state machine -- detect sequence 1101
module fsm(clk,clr,din,dout);
input clk, clr, din;
output dout;
reg dout;
reg[4:0] present_state, next_state;
parameter S0 = 5'b00001, S1 = 5'b00010, S11 = 5'b00100,
S110 = 5'b01000, S1101 = 5'b10000;
clk or posedge clr)
begin
if (clr == 1)
present_state <= S0;
else
present_state <= next_state;
end

28. fsmv.v (cont.) S1 always @(present_state or din) begin S0S1
S11
S110
S1101 1
CLR
or din)
begin
case(present_state)
S0: if(din == 1)
next_state <= S1;
else next_state <= S0;
S1: if(din == 1)
next_state <= S11;
S11: if(din == 0)
next_state <= S110;
else next_state <= S11;
S110: if(din == 1)
next_state <= S1101;
S1101: if(din == 1)
default next_state <= S0;
endcase
end
fsmv.v (cont.)

29. fsmv.v (cont.) always @(present_state) begin
if(present_state == S1101)
dout = 1;
else
dout = 0;
end
endmodule

30. clk_pulse.v module clk_pulse(BTN4, cclk, clr, clk);
input cclk, clr, BTN4;
output clk;
wire clk;
reg delay1, delay2, delay3;
cclk or posedge clr)
begin
if (clr == 1)
delay1 <= 0;
delay2 <= 0;
delay3 <= 0;
end
else
delay1 <= BTN4;
delay2 <= delay1;
delay3 <= delay2;
assign clk = delay1 & delay2 & (!delay3);
endmodule
clk_pulse.v

31. fsmvx.v Top-level design
module fsmx(mclk, bn, SW1, BTN4, led, ldg, LD);
input mclk, bn, SW1, BTN4;
output ldg, led;
output [1:2] LD;
wire [1:2] LD;
wire clr, cclk, bnbuf;
reg [26:0] clkdiv;
IBUFG U00 (.I (bn), .O (bnbuf));
assign led = bnbuf;
assign clr = bnbuf;
assign ldg = 1; // enable 74HC373 latch

32. fsmvx.v (cont.) // Divide the master clock (50Mhz)
mclk)
begin
clkdiv <= clkdiv + 1;
end
assign cclk = clkdiv[17]; // 190 Hz
clk_pulse U0(.BTN4(BTN4),.cclk(cclk),.clr(clr),.clk(clk));
fsm U1(.din(SW1),.dout(LD[2]),.clr(clr),.clk(clk));
assign LD[1] = SW1;
endmodule