1. Designing a Low Power SRAM for PICo
“I LOVE VLSI” ~Benton Calhoun, August 25th 2009
Designing a Low Power SRAM for PICo
ECE4332 : Team 4
Sharif Morad, Maxwell Martin, Jaleesa Boykin, Marc Hall
December 2nd 2009

2. Design Goals Main metric for low power 1Mb SRAM: Requirements:
(Total Power)2 * Delay * Area = (mW2*ns*mm2)
Requirements:
32 bit word size for read or write
Inputs: Address bits, data in, read, write, CLK
Outputs: data out
Functionality at all process corners with various temperatures

3. Array Architecture 16 blocks Block Pre-charging Hierarchical WL
8 words/block
256 x 256 bit cells per block
Block Pre-charging
Hierarchical WL
Shorted BLs/BLBs
Sense Amps

4. Bit Cell
6 xtor bitcell
Calculations and vigorous testing to minimize width

5. Decoders Block SelectHierarchical WLs Decoder Enable Select
Saves Power and Delay
Decoder Enable Select
Saves Power

6. Data Access Shorting BL/BLB
Saves area
MUXing only column blocks saves xtors

7. Sense Amplifier 32 Sense Amps/block column Shorted BL/BLB
Reduce Power
Shorted BL/BLB
Saves area
Saves xtors
Delayed SE signal to wait for BL/BLB data
The read signal is ideal, so in order to match the timing of the two signals, the SE signal is delayed so the data from the BL/BLB is ready to be accepted by the Sense Amp

8. Pre-charge Block BL/BLB shorted Saves Area Hierarchical pre-charge
Only require 4 pre-charge blocks as opposed to 16
Saves Area
6144 xtors
Hierarchical pre-charge
Block Select Signal
Saves Power
Reduces CLK signal load

9. Data Writing Shorting BL/BLB Data xtors for only block column
Saves Area
Data xtors for only block column
Saves 6144 xtors
Column Block Selector
Saves power

10. Further Optimizations
Lower VDD
5V to 2.5V
Reduce Clock period
Reduce ratio width of pre-charge transistors to data write transistors
Clock signal buffering
Used FO4

11. Layout Used past designs Utilized methods to save area Mirroring
Minimum sized gaps

12. Simulation Simulated model of entire array
Extracted bit line and word line R/C
based on layout lengths/widths
Tested and verified functionality at
Process corners (TT, FF, SS, SF, FS)
Different voltages (2.5V, 5V, 5.5V, 4.5V)
Temperature (50C, 27C, 0C)

13. Write 1, Read 1, Write 0 at TT, 2.5V (nominal), 27°C
Results
Write 1, Read 1, Write 0 at TT, 2.5V (nominal), 27°C

14. Metrics Average Power: Delay: Total Area:
~68.916mW
Delay:
72.18ns (worst case delay for read)
Total Area:
Approximately .524mm2
Power Metric: (mW2*ns*mm2)

15. Challenges Tradeoff decisions Wiring/Layout Simulation
Which knobs to turn and amount of sensitivity
Wiring/Layout
Took a long time, changing design was difficult
SKILL may have helped
Magnitude of SRAM
Simulation
Troubleshooting Cadence
Sticking to schedule/time constraints
Server crash

16. Questions?