2. Figure A silicon wafer

3. Figure 1.2 A field-programmable gate array chip
Group of 8 logic cells
Memory block
Interconnection
wires
Figure A field-programmable gate array chip

4. Figure 1.3 The development process
Required product
Design specifications
Initial design
Simulation
Redesign No
Design correct?
Yes
Prototype implementation
Make corrections
Yes
Testing
Minor errors? No No
Meets specifications?
Yes
Finished product
Figure 1.3 The development process

5. Figure 1.4 The basic design loop
Design concept
Initial design
Simulation
Redesign No
Design correct?
Yes
Successful design
Figure The basic design loop

6. Figure 1.5 A printed circuit board

7. Figure 1.6 Design flow for logic circuits
Design concept A
Partition B
Design one block
Design one block C
Design interconnection between blocks
Functional simulation of complete system No
Correct? D
Yes
Physical mapping
Timing simulation No
Correct?
Yes
Implementation
Figure 1.6 Design flow for logic circuits

8. Figure 1.7 Completion of PCB development
Implementation
Build prototype
Testing
Modify prototype
Yes No
Correct?
Minor errors?
Yes No
Finished PCB
Go to A, B, C, or D in Figure 1.6
Figure Completion of PCB development

9. Figure 1.8 The Altera UP-1 Development Board