1. Figure A silicon wafer.

2. Figure 1.2. A field-programmable gate array chip.
Group of 8 logic cells
Memory block
Interconnection
wires
Figure A field-programmable gate array chip.

3. Please see “portrait orientation” PowerPoint file for Chapter 1
Figure The development process.

4. Figure 1.4. The basic design loop.
Design concept
Initial design
Simulation
Redesign No
Design correct?
Yes
Successful design
Figure The basic design loop.

5. Figure 1.5. A printed circuit board.

6. Please see “portrait orientation” PowerPoint file for Chapter 1
Figure Design flow for logic circuits.

7. Figure 1.7. Completion of PCB development.
Implementation
Build prototype
Testing
Modify prototype
Yes No
Correct?
Minor errors?
Yes No
Finished PCB
Go to A, B, C, or D in Figure 1.6
Figure Completion of PCB development.