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Each D type is initiated simultaneously by means of a common clock line.

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Presentation on theme: "Each D type is initiated simultaneously by means of a common clock line."— Presentation transcript:

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6 Each D type is initiated simultaneously by means of a common clock line.

7 S6 S4 S2 4 unused states, ie 001,011,101,111 S7 111 101 S5 011 001 S0
000 S3 110 S1 010 S2 100

8 B A.C B+C

9 Remove the two NOT gates and use the relevant Q output for A and B
S0 (00)

10 goto captain

11 PORTB,1 half PORTB,1 half btfss PORTA,0 goto loop movf Wtemp,0 retfie

12 In the event of an interrupt being initiated it immediately stores the contents of the working register in the temporary register Wtemp. This is because the working register may be used during the ISR and hence its contents changed.

13 0.8V

14 Y X . Y .Z + X . Y . Z

15 Use 7 comparators inputting into the priority- encoder, one comparator inputting into the overflow indicator, 8 resistor voltage divider and a 3 bit output.

16 VLS= = 1.6V Input impedance =hfeRL=50 X 8= 400 ohms Use a resistor divider network to provide positive DC bias Use a push pull power amplifier which will reduce the effect of distortion but still produce crossover distortion

17 V1=12-7.5=4.5V

18 VL( approx) = VZ(1 + RF/R1), Max Value VL=7. 5(1+1/3) = 9
VL( approx) = VZ(1 + RF/R1), Max Value VL=7.5(1+1/3) = 9.98V ( approx 10V) 10V 7.5V VS increases to 13V. Voltage across resistor increases but voltage across zener remains at 7.5V ie output voltage remains unchanged.

19 A B The dummy gauge is included to compensate for any changes in ambient temperature conditions.

20 VA = ( 12/ ) X340 = 6.20V VB = (12/680)X340 = 6V V1= = 0.20V Gain = P/75K, P=75Kx50 =3750K P=3750K 75K R= 3750K Vout = +0.2 X 50 = =10v

21 The thyristor must be Forward Biased
A positive gate pulse of sufficient voltage must be applied.

22 S2 24V V 0V V 0V V

23 VR= = 22V R = VR/Ig = 22/60mA = 367ohms

24 The de-coupling capacitors remove any unwanted DC from the input of the amplifier .

25 √2500 = 50 √2500 =50 BW =GBWP/50 = 1.6x106/50= 32KHz

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27 Max gain on channel 1 =10, 100K/R1
RF= 100K R1 10K Vout R2 20K Gain on each channel is a max when the variable resistor are at minimum value ie = 0 ohms

28 Fb=1/(2∏RC )=133Hz Gain at frequencies above the break frequency =75/15 =5

29 Fb


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