1. Bunch-by-bunch feedbacks and Low Level RF
Alessandro Drago
LNF, 1-4 December 2009

2. Main topics Feedback design basics
12-bit feedback ready to be tested for the new KLOE runs in DAFNE
Low noise longitudinal front-end / back-end ready to be tested for the new KLOE runs in DAFNE
FPGA design progress
Jitter measurements on Virtex-5 FPGA
Models & simulators
Low Level RF status
Conclusions

3. SuperB bunch-by-bunch feedback system general considerations
Dramatic acceleration of electronic component development, is making obsolete in short time ALL the existing DAFNE and PEPII transverse and longitudinal feedback systems (included the last versions), and SuperB commissioning will start not before 2014
Low emittance beams ask for small impact feedback design
From DAFNE tests, we know that it is always possible manage more power in the feedbacks installing as many systems as necessary
Indeed we have proved that two separate feedback systems for the same oscillation plane can work in perfect collaboration doubling the feedback damping inverse time
New feedback design can’t be just a software porting but it must be based on robustness, flexibility, scalability and innovation, and, as consequence, the digital processing unit (DPU) will be the same for transverse and longitudinal feedback systems
New feedback systems needs internal and beam diagnostics tools and the legacy of the previous systems should be carefully implemented with the best compatibility

4. B-B-B Feedback Main R&D Topics
R&D list includes the following upgrade points respect to the previous feedback versions:
very low noise analog front n*RF [n=3 or 4 or 6]
maintain low cross-talk between adjacent bunches under 40 dB (better 60 dB) in front end
Only one pickup for each feedback system
digital processing unit with 12/16bits ADC/DAC for high dynamic range feedback loop >=72dB
“dual gain” approach to minimize residual beam motion and feedback noise on the beam [to be implemented in DPU]
integrated beam-feedback model with easy code and parameter download to DPU
500W vs. 250W power amplifiers
dual separated timing to pilot the backend power stage
Cavity kickers (for longitudinal systems) and stripline kickers (for transverse systems) for 2.1 ns bunch spacing

5. Open questions Type and growth rate of instabilities
How much power & how many feedbacks are necessary ?
Impact of b-b-b feedback systems on ultra-low emittance beams
Obsolescence of the hardware (chips)
Obsolescence of the project (software maintenance)

6. Design progress
Two converging ways to test the design topics: outsourcing R&D and in-house R&D
1.) outsourcing R&D: an upgrade of the iGP system working at 12 bit (iGp12) will be ready by next March to be evaluated at DAFNE for KLOE runs (two units funded by SuperB 2009 budget)
1.1) the iGp12 is sw compatible with the previous 8bit iGp system born by a KEK-SLAC-LNF collaboration
1.2) longitudinal front-end / back-end will be also ready and tested in the next DAFNE/KLOE run (SuperB budget)
2) in-house R&D: a stand-alone development system, using a XILINX single-board, is under test at LNF (funded by INFN C.S.N.V with the SFEED project)
The two approaches are both necessary to evaluate at the best the design parameters versus the real FPGA computing power

7. DAFNE (2010) bunch-by-bunch feedbacks
2.7 ns
bunch
2.7 ns D S
Comb gen.
250W
180
DPU
16bit DAC
FPGA
12bit ADC
250W/500W AM
Phase detector x LP x
a*RF
6*RF
RF (476MHz)
Inj.Trigger
LAN
Operator interface
realtime and offline
analysis programs
DPU
16bit DAC
FPGA
12bit ADC

8. SuperB bunch-by-bunch feedbacks
2.1 ns
bunch
2.1 ns D S
Comb gen.
250W
DPU
16bit DAC
FPGA
12bit ADC
250W/500W AM
Phase detector x LP x
a*RF
6*RF
RF (476MHz)
Inj.Trigger
User trigger
LAN
Operator interface
realtime and offline
analysis programs
DPU
16bit DAC
FPGA
12bit ADC
180 x
Amplitude detector LP
3*RF

9. Differences between SuperB & DAFNE feedbacks
bunch
2.1 ns D S
Comb gen.
250W
DPU
16bit DAC
FPGA
12bit ADC
250W/500W AM
Phase detector x LP x
a*RF
6*RF
RF (476MHz)
Inj.Trigger
User trigger
LAN
Operator interface
realtime and offline
analysis programs
DPU
16bit DAC
FPGA
12bit ADC
180 x
Amplitude detector LP
3*RF

10. In-house R&D Based on XILINX ML506 with Virtex-5 FPGA Main features
The operator interface is based on a Web-Browser through a LAN (1Gbps ethernet) connection (on the contrary in the iGp and iGp12 systems the operator interface is made by EPICS)
The external pc, placed inside the iGp box, is not more necessary because Microblaze microprocessor is implemented in the FPGA itself
Low cost powerful board, commercially available
Easy reprogramming in-house
Many tests of the hardware performance are possible because it is not a black box

12. Web browser Operator interface / I

13. Web browser Operator interface / II

14. General Clock Divider (odd part)
microBlaze
clkout N
extCLK
CNT mod N =
CNT
1+(N-1)/2
en_tff2
FF (toggle)
en_tff1
div1
div2 14

15. Division by 2 done by FPGA by web browser operator interface choice
50MHz input clock
25MHz input clock
25MHz input clock/

16. FPGA divisions by 3x2 by 4x2 by 5x2

17. Jitter measurements

18. Jitter measurements made by high bandwidth (20GHz) oscilloscope TEK 11801A making a comparison between source RF signal and division reasult output signal
~40 ps
peak-peak jitter
~5 ps
RMS jitter

19. Models & simulators
It is necessary to define power and number of feedback systems: to do this the known data should be inserted in a model/simulator
Simulator 1) DAFNE itself
Simulator 2) longitudinal beam/RF/feedback simulator, written in FORTRAN, used for DAFNE (in ) to be revised
Simulator 3) instability / feedback simulator, written in Simulink/Matlab
Simulator 4) in base at the e-clouds models

20. Simulator 2) longitudinal beam/RF/feedback simulator, written in FORTRAN, used for DAFNE (in ) to be revised for the SuperB case
Analytical approach
Small oscillations
Equispaced bunches
Equal charge bunches
Produce an output tracking for longitudinal oscillation of each bunch

21. Mauro Migliorati (Roma1 University) has made the porting from the original FORTRAN code running for VAX/VMS to PC/Windows without any problems [November 2009]
In principle the program can run on every PC from the Command Prompt windows
To start the SuperB simulation, we need machine parameters and the PEPII Cavity High Order Modes, then check if the approximations in the code are enough good

22. .FOR  source files
.inp  input files
.exe  executable file
.out  output file
.dat  tracking data files
Compiler: G77 for Windows
Cygwin1.dll library for windows interface

23. cav-mac.inp  cavity-machine input data file

24. .out output file

25. Easy file.dat data plot by MATLAB

26. Low Level RF status
obsolescence of the old PEP-II subsystem is obvious
up to now we have considered two very different ways to implement this subsystem
1) Dimtel Inc. & Larry Doolittle approach consist in design a LLRF board to be so flexible to cope with “any” unknown specifications
2) in the second approach, LPSC [ Laboratory of Subatomic Physics and Cosmology] - IN2P3/CNRS laboratory in Grenoble/France (O. Bourrion & C. Vescovi) is ready to start a design after some knowledge of specifications. They are currently working on the LLRF of CNAO (Pavia, Italy) system that should become operative in next months
CNAO RF specifications are not very similar to the SuperB ones
At the present we need to write of the subsystem specification or, at least to have an idea of them, to go ahead

27. Conclusions
Much work is in very quick progress for the bunch-by-bunch feedback
Next DAFNE runs will be important to evaluate what is still necessary for the final b-b-b feedback implementation
Some work on the longitudinal simulator can start just from now
LLRF design is waiting for spec’s