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JTAG feature nan FIP Stephen Page TE/EPC-CC

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Presentation on theme: "JTAG feature nan FIP Stephen Page TE/EPC-CC"— Presentation transcript:

1 21.07.2011 JTAG feature nan FIP Stephen Page TE/EPC-CC
Eva Gousiou BE/CO-HT & the nanoFIP team nan FIP

2 Outline Introduction SW and HW implementations Simulations & Testing
Next Steps

3 Outline Introduction SW and HW implementations Simulations & Testing
Next Steps

4 Introduction The purpose of the JTAG feature is the possibility to reprogram an FPGA through nanoFIP. Each equipment device will be composed of a nanoFIP and an application-specific user FPGA There will be more than 3000 such devices distributed around the LHC Given the difficulty of accessing the equipment, it will be efficient to be able to remotely reprogram the user FPGAs. user user JTAG FIELDBUS

5 JTAG for ISP introduction
IEEE JTAG interface originally intended for boundary scan All main FPGA manufacturers have developed In-System Programming capability for remote programming & verification through JTAG All JTAG operations are controlled through the device’s Test Access Port (TAP) TCK TAP TAP Controller FSM TMS TDI TDO IEEE defines the behavior of the TAP state machine and its outputs according to specified activities on the inputs State transitions occur on the TCK TMS input value determines the next state TDI input value is sampled at the TCK TDO output is updated on the TCK TAP Controller

6 Serial Vector Format svf bin
SVF is a programming ASCII file format for storing the patterns that should be sent to the JTAG interface, as well as the expected response svf Actel, Xilinx and Altera tools support the direct generation of SVF files PAR bin SVF does not describe the explicit state of the JTAG system on every TCK cycle; it describes it in terms of transactions conducted between certain states Each SVF command has to be translated to the equivalent sequence of TCK, TMS, TDI and expected TDO that will control the state of the TAP Controller For the nanoFIP project the interpretation is done in SW

7 Outline Introduction SW and HW implementations Simulations & Testing
Next Steps

8 Considerations During the reprogramming process, the normal gateway tasks will be stopped Reprogramming will only be used without LHC beam ProASIC3 devices can be reprogrammed before the accumulation of ~100 Gy

9 JTAG programmer SW Master .svf Lib(X)SVF TMS TDI TDO TMS TDI
During the reprogramming process, the normal gateway tasks will be stopped Reprogramming will only be used without LHC beam ProASIC3 devices can be reprogrammed before the accumulation of ~100 Gy Master Lib(X)SVF ISC TMS TDI TDO TMS TDI

10 JTAG programmer SW Master .svf Lib(X)SVF TMS TDI TDO TMS TDI TMS TDI
ISC TMS TDI TDO TMS TDI TMS TDI TMS TDI …

11 JTAG programmer SW Master .svf Lib(X)SVF TMS TDI TDO TMS TDI TDO
ISC TMS TDI TDO TMS TDI TDO FSS Ctrl TMS TDI TMS TDI TMS TDI … CRC FES

12 JTAG programmer SW Master .svf Lib(X)SVF TMS TDI TDO TMS TDI … FES
ISC user TMS TDI TDO TMS TDI … CRC FES Ctrl FSS FIELDBUS

13 JTAG Controller HW user Master Field TR Fiel drive FIELDBUS

14 JTAG Controller HW user Cons Master Field TR Fiel drive FIELDBUS

15 JTAG Controller HW TAP Cons TCK user TMS TDI Prod TDO FIELDBUS Master
drive FIELDBUS

16 JTAG Controller HW TAP Cons TCK user TMS TDI Prod TDO FIELDBUS Master
drive FIELDBUS

17 Timing 2.5Mb Mb Kb Actel 400K gates programming: m59s 3m56s h21m40s Actel 400K gates verification : m03s 1m26s m39s Actel 250K gates programming: m53s 3m33s h10m57s Actel 250K gates verification : m02s 1m23s m17s Xilinx 11K2 slices programming: m23s m14s h04m57s

18 Outline Introduction SW and HW implementations Simulations & Testing
Next Steps

19 Simulations & Testing validated with independent Simulation Test Bench by G.Penacoba (TE/CRG.) nan FIP Thousands of programming/verification cycles of ProASIC3 & Virtex5 FPGAs nanoFIP programming the User FPGA nanoFIP programming another nanoFIP nanoFIP programming a Virtex5

20 Simulations & Testing validated with independent Simulation Test Bench by G.Penacoba (TE/CRG.) nan FIP Thousands of programming/verification cycles of ProASIC3 & Virtex5 FPGAs user Xilinx nanoFIP programming the User FPGA nanoFIP programming another nanoFIP nanoFIP programming a Virtex5

21 Outline Introduction SW and HW implementations Simulations & Testing
Next Steps

22 Next steps Documentation and User’s Manual
Continue testing (including Altera FPGAs) code review nan FIP radiation tests nan FIP

23 Extras

24 Introduction … More than 10.000 ….bla bla bla… Master user user user
WB slone user user user WB slone user user WB slone JTAG JTAG JTAG … FIELDBUS More than ….bla bla bla…

25 Project Organization & Some History
Concerns for the long-term availability of ALSTOM’s components; WorldFIP Taskforce set up. (2006) Taskforce conclusions: No technological alternative & in-sourcing of WorldFIP technology (2007) ALSTOM-CERN contract with CERN purchasing ALSTOM’s design information (2008) Project divided in different Work Packages: (2009) WP1: microFIP code preliminary interpretation (B. Todd, TE/MPE & E. van der Bij) WP2: project management documentation for the in-sourcing (E. van der Bij) WP3: functional specifications for microFIP’s replacement (E. van der Bij) WP4: rewrite & extend microFIP VHDL code WP5: write new code (P. Alvarez & E. Gousiou) WP6: test bench creation (G. Penacoba, TE/CRG) WP7: design of a board for functional and radiation tests (HLP, France) WP8: Radiation tests (CERN RadWG EN/STI & E. Gousiou)

26 WorldFIP Frames Communication throughput for 1Mbps: FSS Ctrl Id CRC
Master -> nanoFIP FSS 2 bytes Ctrl 1 byte Id CRC 2 byte FES 8 bytes * 8 bits* 1 us turnaround time 10 us 10 us nanoFIP -> Master FSS 2 bytes Ctrl 1 byte Data 124 bytes CRC 2 byte FES 130 bytes * 8 bits * 1us 1.1 ms for 124 data-bytes = 0.9 Mb/s Master -> nanoFIP FSS 2 bytes Ctrl 1 byte Id CRC 2 byte FES turnaround time 10 us 138 us for 2 data-bytes = 0.1 Mb/s FSS 2 bytes Ctrl 1 byte Data CRC 2 byte FES nanoFIP -> Master

27 Project Status Majority voter circuit:

28 Functionalities & Features
WorldFIP services: Consumption of one addressed variable (up to 124 bytes) Consumption of one broadcast variable (up to 124 bytes) Production of one addressed variable (2, 8, 16,..,124 bytes) user WorldFIP Master nFIP consumption production

29 Functionalities & Features
WorldFIP services: Consumption of one addressed variable (up to 124 bytes) Consumption of one broadcast variable (up to 124 bytes) Production of one addressed variable (2, 8, 16,..,124 bytes) user WorldFIP Master nFIP consumption production Simple interface with the user: Data transfer over an integrated memory or user WISHBONE MEMORY nanoFIP

30 Functionalities & Features
WorldFIP services: Consumption of one addressed variable (up to 124 bytes) Consumption of one broadcast variable (up to 124 bytes) Production of one addressed variable (2, 8, 16,..,124 bytes) user WorldFIP Master nFIP consumption production Simple interface with the user: Data transfer over an integrated memory or user WISHBONE MEMORY nanoFIP Data transfer in stand-alone mode (2 bytes data exchange, no need for memory access). 16 bit DATA BUS

31 Functionalities & Features
WorldFIP services: Consumption of one addressed variable (up to 124 bytes) Consumption of one broadcast variable (up to 124 bytes) Production of one addressed variable (2, 8, 16,..,124 bytes) user WorldFIP Master nFIP consumption production Simple interface with the user: Data transfer over an integrated memory or user WISHBONE MEMORY nanoFIP Produced Var Ready! Consumed Var. Ready! ConsumedBR Var. Ready! Data transfer in stand-alone mode (2 bytes data exchange, no need for memory access). 16 bit DATA BUS Separate “data valid” outputs for each variable.

32 Functionalities & Features
WorldFIP services: Consumption of one addressed variable (up to 124 bytes) Consumption of one broadcast variable (up to 124 bytes) Production of one addressed variable (2, 8, 16,..,124 bytes) user WorldFIP Master nFIP consumption production Simple interface with the user: Data transfer over an integrated memory or user WISHBONE MEMORY nanoFIP Produced Var Ready! Consumed Var. Ready! ConsumedBR Var. Ready! Data transfer in stand-alone mode (2 bytes data exchange, no need for memory access). 16 bit DATA BUS Separate “data valid” outputs for each variable. overview Features: Communication in 3 speeds: 31.25kb/s, 1Mb/s, 2.5Mb/s. Independent memories (124 bytes each) for consumed and produced data. nanoFIP status byte available to the User and the Master.

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