1. APiX Development of an Avalanche Pixel Sensor
CdS INFN Padova
2014/6/30
P.Sartori
per G.Collazuol
APiX
Development of an Avalanche Pixel Sensor
for Tracking Applications
INFN Pisa (2.6FTE): P.S. Marrocchesi (resp. nazionale), M.G.Bagliesi, G.Bigongiari, S.Bonechi, P. Brogi, P. Maestro, F. Morsani, F. Pacciani, J.E.Suh, A. Sulaj
INFN Padova (0.2FTE): G.Collazuol (resp.loc.)
INFN Pavia (1.0FTE): L.Ratti (resp.loc.), C.Vacchi
TIFPA Trento (1.5FTE): G.F.Dalla Betta (resp.loc.), L.Pancheri, S.Zucca
Note:
International institutions:
A. Savoy Navarro, C.S. Moon
Laboratoire APC , Université Paris-Diderot/CNRS
V. Saveliev, N. D’Ascenzo
Institute of Applied Mathematics, Russian Academy of Science, Moscow, Russia

2. Motivation Innovative Silicon tracker based on
1) thin sensitive volumes (pixels)
2) producing large signals
3) high timing resolution
reduced material budget
reduced power consumption
enhanced S/N with “simple” electronics
better radiation hardness
high rate capability
Note:
G.Collazuol - APIX

3. Overview The APiX concept
• CMOS avalanche cells providing internal gain
for charged particle detection
• Coincidence between vertically aligned cells pairs
to drastically reduce Dark Count Rate (DCR):
→ dual tier Avalanche PiXel detector
Main technological challenges:
1) CMOS sensor design:
optimized for charged particle detection
starting from the experience with CMOS SPAD development
2) Vertical integration of electronics for signal processing
Mature technology:
3) Thinning
4) Readout architecture
Workplan and milestones
Note:
G.Collazuol - APIX

4. Basic detector element
The basic element of the APiX detector is an avalanche diode
based on a CMOS process and operated in quenched Geiger mode
- Several possible implementations in standard CMOS or CMOS imaging (CIS) or CMOS HV technologies
- Inheritance from CMOS SPAD detector design
Example: p+/n active area junction
+ Guard Ring + buried isolation layer
Note:
 Large internal gain provided by the detector itself → no pre-amplification → less power
 no amplitude measurement, pure binary information (hit/no hit)
 sensitive layer of the device is very thin, limited to the depleted region around the pn junction
→ virtually no charge loss if the substrate is thinned down.
 readout electronics integrated in the same substrate as the sensor
BUT
- an avalanche detector is affected by a large dark count rate DCR ~ O(100 kHz/mm2)
APiX concept: the coincidence of vertically aligned cells drastically reduces DCR problem
G.Collazuol - APIX

5. APiX concept: dual tier Avalanche pixel detector
Goal: reducing Dark Rate effects by using coincidence between two overlapping pixels (sensor pairs)
Accidental coincidence rate (estimate)
Assuming a dark count rate DCR = 100 kHz/mm2 and
Δt = 10ns coincidence, with N=50 μm x 50 μm pixels,
the rate of fake 2‐fold coincidence is
2 R2 Δt/N = 0.5 Hz/mm2
For 1cm2 detector is would be close to 50 Hz
Main assets:
Internal Gain
→ reduces dramatically the material budget (few mm sensitive thickness)
Readout electronics on chip → digital signal out
→ reduction of the power consumption
Vertical alignment and coincidence
→ overcome the dark rate probability and sensitivity to photons
Flexibility in layout → improving detection efficiency for ionizing particles
Note:
Sensor Power consumption (readout power excluded)
Assuming a 100MHz/cm2 hit rate on 1cm2 detector,
the average current = 106
i.e. a power dissipation of about 0.32 mW/cm2
for 2 layers in the case of 10 V bias in the cell for
full avalanche operation
G.Collazuol - APIX

6. 1) Main technological challenges: CMOS implementation
Implementation goals in CMOS for APiX are similar to
the ones for CMOS SPAD (photon sensor):
1) minimize the Dark Count Rate (DCR)
• in deep‐submicron technologies band‐to‐band tunneling typically increases due to the
heavy doping concentration in the well implants → increases DCR
• Shallow Trench Isolation (STI) oxide defects in Si interface → DCR generation centers
• care must be taken in designing the Guard Ring structures
2) maximize detector efficiency
For photon detection (as in the case of CMOS SPAD, SiPM) this means to maximize the
Photon Detection Efficiency (PDE). However, in the case of particle detection (as
proposed by APiX) photo‐absorbent structures limiting the Fill Factor (FF) are a minor
issue. The layout can afford opaque structures (e.g. quenching resistor, poly lines, etc.)
that are practically transparent to ionizing radiation
Note:
Example of implementation of CMOS SPAD
in 150nm CMOS process available at LFoundry:
circular and square 10 um SPAD
L. Pancheri, D. Stoppa, “Low‐noise single Photon
Avalanche Diodes in 0.15μm CMOS technology”,
IEEE Proc. of ESSDERC11 pp. 179‐182 (2011)
Technologies by LFoundry and XFAB
will be exploited
G.Collazuol - APIX

7. 2) Main technological challenges: Vertical integration
Vertical integration seems a natural choice for
fabrication of a dual‐tier avalanche pixel sensor
Virtually monolithic integration
with chip‐to‐chip, chip-to-wafer,
wafer-to-wafer vertical
interconnection
Various interconnection
techniques available:
micro‐bump bonding,
direct bond interconnect,
thermo compression
Note:
Technologies by Tezzaron Semiconductor and Tohoku MicroTec (T-Micro) will be exploited
G.Collazuol - APIX

8. 3) Mature technologies: Sensor thinning
Improves momentum resolution by reducing multiple scattering in
multilayer silicon sensors
Different approaches are available
to thin wafer down even to 1mm
→ based on oxide or p++ layers
acting as etch stoppers
Note:
Aptek Industries offers
thinning services down to
25‐30 mm (10‐15 mm
with 30% yield)
at quite low prices
($ 30 per die, $ 287
minimum)
G.Collazuol - APIX

9. 4) Mature technologies: Readout electronics
Very simple front‐end:
TOP LAYER: converting the detector signal to a CMOS logic level
BOTTOM LAYER: coincidence logic and r/o interface
Note:
G.Collazuol - APIX

10. Applications
The main goal of the project is the development of a detector for
tracking (vertexing) applications, with low-material budget and low-power consumption;
Use of CMOS technology ensures that high performance digital readout
circuits can be monolithically integrated with the sensitive part of the device
Note:
The outcome of this R&D activity can be beneficial to a number of other fields, including:
• research instrumentation;
• biomedical applications (e.g.: with beta-emitters);
• electron microscopy;
• CMOS imagers;
• other (industrial quality controls, homeland security, ...)
G.Collazuol - APIX

11. Workplan and Milestones
First year • simulation and design of avalanche pixel sensors (different pixel options for performance optimization) • modeling of the vertical interconnected structure • prototype fabrication and test • vertical integration • design of a multipurpose lab test bench Second year • development of a small, vertically integrated detector prototype with integrated readout electronics • test on a particle beam • study of radiation tolerance of the device (from the standpoint of both ionization and bulk damage) Third year • development of an APiX chip building block with relatively large active area • test on a particle beam
Milestone
development of
- basic sensor and
- test structures of
vertically aligned
cell pairs
fabrication and
test of the APiX
digital sensor
building block
Note:
Note: Delayed approval procedure for APIX in INFN
→ time zero ~ spring 2014
G.Collazuol - APIX

12. APIX Padova PC links FPGA
Readout and
Control
Interface
Board
FPGA
APIX Padova will take care of Readout and Control Board:
- ReadOut and digital processing by FPGA
- Control by mcontroller/FPGA
→ needed for instance to set SPAD enable mask (each SPAD can be
enabled/disabled in case it generates too much DCR) or trigger configuration
APIX Padova will contribute also with simulation of detector physics
Nota: Tesi triennale Tommaso Boschi (relatore G.C.) “Studi per lo sviluppo di tracciatori di particelle basati su pixel di silicio in regime Geiger”
→ effetti di particelle ionizzanti in Silicon PM
Note:
G.Collazuol - APIX

13. APIX Padova – Richieste 2015
Personale:
G.Collazuol al 20% → resp. loc. “APIZ2_DTZ”
Richieste budget 2015:
Missioni estere k€
→ test beam CERN
Consumo k€
→ scheda elettronica readout per test primi chip
Note:
Richieste servizi locali:
Elettronica: 3 m.u. per disegno e realizzazione scheda
Progettazione Meccanica: ¼ m.u. per struttura test beam
Officina Meccanica: ¼ m.u. per struttura test beam
G.Collazuol - APIX