1. Other Approaches

2. The Way Transistors Are Really Used
Transistor gates presented before uses power whenever voltage is connected to ground!

3. NOT Gate One transistor
V (high voltage)
Out
In = high, switch is closed
so current flows to ground
Out is low. In
In = low, switch is open
so current flows to Out
Out is high.

4. NOR Gate Two transistors
V (high voltage)
Out
In 1
In 2

5. CMOS transistors Complementary Metal Oxide Semiconductor
Replaces single transistors with a pair, one p-type (like we used), one n-type (current passes when control is low)
Set up so that in steady state, no current flows to ground
Only uses power when switching

7. CMOS circuits use far less power – the current main constraint on the development of faster cpus.
Since 1976 the better power saving technology
Most processors today use this technology

8. Do We Really Need A Clock?
Standard computer architecture, virtually all computers use a clock
Problems:
Clock skew – as the clock signal propagates through the circuit, it hits elements distant from the source later than one close. Can cause problems.
Length of clock cycle depends on longest latency in a phase of circuit.
Some phases might be able to execute faster, balancing is hard
In a phase, some operations might be able to execute faster than others (for example, AND vs ADD in an ALU)
Alternative ?

9. Asynchronous circuits
No clock
Signals move from one component to another by a signaling system
Component with information to pass “forward” in the system send a request signal to the component to receive, setting up the data to send at the same time.
Component receiving replies with an acknowledgement when it has received the data, letting the sender know it can remove the data from the channel
Receiving Component will process the data, then communicate with next component in a similar manner.
A chain of such elements will comprise an asynchronous circuit.
The request/acknowledge combination is called a “handshake”

10. Handshake Req Ack Sender sets up data on Data channel
Sender sends request on Req wire
Receiver reads data into latch
Receiver sends acknowledge on Ack wire.
Sender
Receiver
Data
Ack
Req

11. 2-Phase protocol each level change is a req/ack
Req Req Req3
Data Data Data3
Ready Ready Ready
Sender
Receiver
Ack Ack Ack3
Data1 received Data2 received Data3 received

12. 4-Phase protocol return to zero before next handshake
Req1 Req1 down Req2 Req2 down
Data Data2
Ready Ready
Sender
Receiver
Ack Ack1 down Ack Ack2 down
Data1 received ready for more Data2 received ready for more

14. When can we pass data forward?
Bundled Data
Fixed delay
Needs to be as long as longest possible processing time
Sensitive to conditions that may change signal times (like temperature)
QDI (Quasi-Delay Insensitive)
Determine when computation is complete
Time only needed for this computation
Needs more logic

16. QDI -- how to detect completion
Each bit has two signal wires:
Bottom wire is actual bit value
Top wire is negation of top
When both are zero, no data established
When both are one, invalid data
Value = 0 Value = 1 Completion for one bit detected
D0 = D0 = when D0 XOR D1 = 1
D1 = D1 = 1
Completion for several bits when all
one bit XOR’s are 1 – use AND gates

19. MiniMIPS An Asynchronous implementation of MIPS R3000 architecture
Cal Tech, 1998
Used small QDI components
Multiple execution units
Performance 2 ½ to 4 times better than equivalent clocked technology