1. ATLAS calorimeter and topological trigger upgrades for Phase 1
Samuel Silverstein, Stockholm University
For ATLAS TDAQ/L1Calo
+ Overview
+ Upgrade to PreProcessor MCM
+ Topological trigger

2. Current L1Calo system DAQ RODs E/g t/had RoI clusters RODs (CP) Pre-
Read-out drivers
(RODs)
DAQ
RODs
Input/output data
To DAQ
.1 x .1
Trigger
towers
RoI
RODs
E/g t/had
clusters
(CP)
From
calorimeters
To CTP
To L2
(ROIB)
Pre-
Processor
(PPr)
Analog
tower sums
(0.1 x 0.1)
Jet / SET
(JEP)
.2 x .2
Jet elements
To ROI builder:
jet & cluster RoI
thresholds and
coordinates
Real-time output to CTP:
multiplicities of Jet, EM/t
cluster threshold bits
Digital algorithm processors

3. Phase I upgrades to L1Calo
PreProcessor:
New mixed-signal MCM with FPGA
Topological processing
Add RoI coordinates and additional information to the real-time data path
Topology-based algorithm processor for L1Calo (plus Muon) RoIs

4. PreProcessor MCM functionality
ADC
FIR filter
(5 samples)
(1/4)
Analog trigger
tower sum
0.1  0.1
Peak finder
Used to identify bunch crossing
No consecutive
non-zero values
To CP
serialiser
To JEP
(4x4) 
serialiser

5. New PreProcessor MCM
FPGA-based replacement for existing mixed-signal MCM
Motivations
Drop-in replacement if failure rate higher than expected
Possible to upgrade digital processing algorithms, e.g.
Improve BCID algorithms
Compensate for baseline shifting at high luminosity
Features
Two dual-channel FADCs (AD9218)
Lower power consumption/channel
Run at 80 MHz clock rate (latency reduction)
Replace several digital chips with single FPGA (Spartan 6):
Adjustable fine delay for ADC clocks
PreProcessor ASIC
480 Mbit/s LVDS serialisers to CP and JEP

6. PreProcessor MCM upgrade
New MCM
Bottom
Top
FPGA (Spartan 6)
4 ADCs
serializers
2 Dual-channel FADCs (AD9218)
ASIC
Adjustable delay
Current MCM

7. Topological processing
Motivations
Reduce rates while saving physics efficiency
Current triggers are multiplicity based
Higher thresholds lose physics, less effective with pileup
Minimum changes to L1Calo system, rest of experiment
Adding topology to L1Calo:
Keep present data granularity, Jet and EM/ cluster algorithms
Add RoI coordinates and information to real time data path
New firmware in existing processor modules
Higher backplane speed to increase RTDP bandwidth
Replace data merging modules in crates with new boards
Receive and process high-speed backplane data
Send RoIs to topological processor (TP) over high-speed links
Topological processor (TP)
New subsystem (preferred solution)
Pipelined, fixed-latency processing of all RoIs (L1Calo + Muon)

8. Jet and cluster algorithms
EM cluster algorithm
(/had similar):
Jet algorithm:
0.4 x 0.4
0.6 x 0.6
0.8 x 0.8
Local maximum
"Environment"

9. Digital algorithm processors
JEM
JEP: 2 crates
CP: 4 crates C P U M T
14 CPMs C P U C M C M T C M
16 JEMs
Two quadrants
per crate
One quadrant
per crate
CPM
2 merger modules (CMM) collect real-time results from all CPMs/JEMs in the crate

10. Data merger module: CMM
25 point-to-point backplane links from each JEM/CPM to each CMM
Current speed 40 MHz (25 bits/BC)
e.g. 8  3-bit multiplicities + 1 Parity bit
CMM
Backplane
merger layers
Readout To
CTP
System-level
merging
Crate-level
merging

11. Higher backplane bandwidth
Backplane can run at >320 Mbit/s (8  current)
(given fast transmitter, optimum termination)
Actual limit: FPGA outputs on CPM and JEM
Both work well at 160 Mbit/s (4  current)

12. Transmission tests JEM to BLT: Backplane Eye > 3.7 ns link tester
at 160 MHz
Backplane
link tester
(BLT)
Clock and parity
encoded together
on bit 25:
160 MHz transmission
from CPM

13. Adding RoIs to backplane data
Example: proposed 96-bit jet output
4  24 bits at 160 MHz (25th bit used for clock + parity)
8 "presence bits" (Which of the 8 subregions had an RoI?)
Report up to 4 RoIs (expect < 2 per JEM)
2 fine position bits (localize jet to 0.2  0.2 coordinates)
8 threshold bits
Up to 12 additional bits per RoI
For example, jet ET P1 P2 P3 P4 P5 P6 P7 P8
Threshold bits RoI 1 (8b)
Threshold bits RoI 2 (8b)
Fine Pos RoI 1
Fine Pos RoI 2
Fine pos RoI 3
Fine Pos RoI 4
Threshold bits RoI 3 (8b)
Threshold bits RoI 4 (8b)
Jet RoI 1 ET (12b)
Jet RoI 2 ET (12b)
Jet RoI 3 ET (12b)
Jet RoI 4 ET (12b)

14. CMM replacement: CMM++
VME --
VME
CPLD
Readout to DAQ and ROI RODs
(Glink emulation)
Optical links:
12-fiber bundles
(SNAP12 or
or similar),
6.4 Gbit/s
SNAP12
Virtex 6
HX565T
LVDS links for crate-to-
system
merging
SNAP12
SNAP12
SNAP12
Backplane
data from
JEMs/CPMs
(160 MHz)
LVDS outputs
to CTP
SNAP12
Must be backward-compatible with existing CMM 14 14

15. CMM++ firmware studies
Device: Virtex 6
(XC6VHX565T-2FF1924)
VME--
VME
CPLD
Glink
DAQ and ROI readout
TTCrx
Glink
Backward-compatible
Jet firmware, including
jet and system FPGAs,
emulated Glinks
(based on production
CMM VHDL code)
Virtex E
(crate)
Virtex E
(system)
"Legacy" design uses
~ 2% of internal resources;
Plenty of room left....
2-3x faster than Virtex E 15 15

16. Topological processor (TP)
Two options being considered:
Preferred: New topological processor (TP) subsystem
Modern technology / form factor (Virtex 6/ATCA)
Receive and process all L1Calo RoIs
Able to include Muon RoIs
Backup: Topological algorithms in CMM++
Connect fiber links in a star configuration, with one CMM++ as the TP
Process all jet, CP RoIs
No room for muon RoIs
More limited algorithm processing (less scalable)

17. TP subsystem (preferred)
E/g t/had
clusters
(CP)
Muons
0.1 x 0.1 TP To
CTP
Pre-
Processor
(PPr)
Analog
tower sums
(0.1 x 0.1)
Clusters
Jet / SET
(JEP)
0.2 x 0.2
Jets
Energy results to CTP?

18. TP technology demonstrator
TP will almost certainly be simpler. Goal of demonstrator is to encounter and learn from problems with high density, high-power ATCA boards

19. Backup: TP in designated CMM++
EM/ EM
Energy
Jet
EM/ EM
CP1 C M + C M +
JEP0 C M + C M +
CP0 C M + C M +
CLUSTER
JET
ENERGY
LVDS C M +
CP3 C M + C M +
JEP1
(TP) C M + C M +
CP2 C M +
~56 L1Calo fibers to "TP"
(fits in single Virtex-6 HXT)
Note: Not enough room for muon ROIs

20. Summary and status PreProcessor MCM replacement CP/JEP crates
ASIC code ported to Spartan 6 FPGA, plus serialiser and clock manager functionality
PCB layout complete and sent out, expect boards back soon
CP/JEP crates
Backplane transmission tests at 160 MHz look good
Studies indicate upgraded firmware in CPMs and JEMs will easily fit and run at full speed
CMM++ specifications in early stage, studies of prototype firmware look promising
Topological Processor (TP)
Two options (CMM++ or new TP crate)
Technology demonstrator layout nearly complete, soon available for testing