1. Jinfan Chang Experimental Physics Center , IHEP Feb 18 , 2011
KM2A electronics
Jinfan Chang
Experimental Physics Center , IHEP
Feb 18 , 2011

2. Outline Introduction: Tasks and Requirements Design options
Engineering array electronics
waveform digitalization

3. KM2A electronics design include
Ground Electron Detector Array (GEDA) electronics 5137 channels
Ground Muon Detector Array (GMDA) electronics 1209 channels

4. Single channel hit rate
Requirement
Item
GEDA
GMDA
Number of channels
5137
1209
Dynamic Range
1-3000e
1-3000u
Resolution
Timing resolution
2ns
10ns
Single channel hit rate
1KHz
10KHz
threshold
0.25e
0.25u
Operating range
-40 to 80℃

5. Tasks
In order to make the readout electronics system simple and easy to maintain, the same electronics boards will be used for both GEDA and GMDA
Electronics system Functions:
Determine the charge (energy) of each PMT signal
Provide precision timing information (PMT hit to trigger)
Provide real time NHIT (number of PMT hits) to Trigger

6. Design options Charge measurement Time measurement Charge integrate
waveform digitize
Time measurement
TDC using FPGA
Waveform digitize

7. Charge measurement charge integrator: V is proportional to Q
A CR-(RC)n shaping circuit is used to obtain a smooth signal peak
The shaped signal is sent into two amplifiers with different gains, these two analog signals are digitized using two Flash ADCs
The digitized samples go directly into the FPGA, in which all data processing (e.g. range selection, data pipelining, peak finding, pedestal subtraction, nonlinearity corrections, and data buffering) will be implemented

8. Time measurement
A stable threshold is set using a DAC controlled from the FPGA.
The rising edge of the discriminator output signal is used to start the TDC
The trigger signal is used as common stop

9. Time measurement
The TDC will be realized by using internal resources of a high-performance FPGA
The odd counter changes at the rising edge of an internal 320 MHz clock, while the even one changes at the falling edge
Each time bin is ns. The RMS of the time resolution is less than 0.5 ns
Need the less resource of FPGA

10. Engineering array electronics
3 FEE modules (each 16 channels),1 Trigger module,1 GPS module, FEE and Trigger are VME modules
The input PMT signal is immediately amplified and used to drive two distinct circuits, a discriminator (threshold decision and TDC start pulse), and a pulse shaping circuit whose output is sampled to accurately measure the charge of the pulse.

11. VME crate has been put in the center of the array
Fig. Sketch map of the engineering array (42 casstters) in ARGO central carpet. (each red star represents one cassette)
VME crate has been put in the center of the array
The cable length between PMT and FEE is 45m

12. FEE test in Lab Linearity test Time resolution Crosstalk Data transfer
Engineering array test result (see Shengxiangdong’s report and Liujia’s report)

13. Charge measure test High gain: 1pc –100pc Low gain: 100pc – 2800pc
Resolution:

14. Time Resolution
Max time rms is 0.5 TDC count, is *0.5 = 0.78ns

15. Crosstalk ADC Input to ch3 2.5V Input to ch4 No observable xtalk

16. CBLT readout timing test
37 words (36data words + double CBLT foot) needs 12.5us
Speed ： 3.0M words /sec

17. Local station consist of 19 PMTs, each FEB has 19 channels for 19 PMTs
GPS
hexagon
Local station consist of 19 PMTs, each FEB has 19 channels for 19 PMTs
The cable length between PMT and FEB is 30m
The local station will collect the Muon detector data which in the area
FEB data will be transferred from local station to center station

18. Waveform digitization
PMT signal
Rising edge :~3ns
After 30m cable
Rising edge :4ns~5ns
FADC: E2V AT84AS001
12bit 500Msps
Power consumption 2.4W
ENOB 10bit

19. Waveform digitization prototype module
Waveform digitization can save all the information from PMT output signal
No dead time, can distinguish different signal and pileup

20. Prototype status
Waveform digitization module and data receiver module: schematic design has finished
After technical review, start to PCB layout

21. Time calibration Local station Center station
Center station clock is synchronized by GPS
Center station generate a pulse to FDB board at time t1;FDB return a pulse after a known, programmable wait interval δt; center station board received the return pulse at time t2
T1,T2,and δt are known, we can get the relationship between local time and center time by a certain arithmetic
Clock distribution: “white rabbit” (see Duqiang’s report)

22. Trigger There are n PMTs firing in trigger windows
N will be decided by simulation and experiments
Trigger windows is 1us

23. KM2A electronics design
Possible option
ASIC chip (see Yanxiongbo’s report)

24. Thank you！ Any suggestion is welcome !