1. Introduction to CMOS VLSI Design

2. Before we start…. In this module we are going to study
NMOS and CMOS Design Styles
Both combinational and sequential
(We had done many examples in our class.So Please go on that.Here I am giving the design of basic gates only)
Stick Diagrams
Layouts
Lamda and micron design rules

3. Transistors as Switches
We can view MOS transistors as electrically controlled switches
Voltage at gate controls path from source to drain

4. CMOS Inverter A Y 1

5. CMOS Inverter A Y 1

6. CMOS Inverter A Y 1

7. CMOS NAND Gate A B Y 1

8. CMOS NAND Gate A B Y 1

9. CMOS NAND Gate A B Y 1

10. CMOS NAND Gate A B Y 1

11. CMOS NAND Gate A B Y 1

12. CMOS NOR Gate A B Y 1

13. VLSI design aims to translate circuit concepts onto silicon.
stick diagrams are a means of capturing topography and layer information using simple diagrams.
Stick diagrams convey layer information through colour codes (or monochrome encoding).
Acts as an interface between symbolic circuit and the actual layout.

14. Stick diagrams A stick diagram is a cartoon of a layout.
Does show all components/vias (except possibly tub ties), relative placement.
Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.

15. Stick Diagrams Key idea: "Stick figure cartoon" of a layout
Useful for planning layout
relative placement of transistors
assignment of signals to layers
connections between cells
cell hierarchy

16. Stick Diagrams (3/3)

17. Stick Diagrams – Notations
Metal 1
Can also draw
in shades of
gray/line style.
poly
ndiff
pdiff
Similarly for contacts, via, tub etc..

18. Stick Diagrams – Some rules
Rule 1. When two or more ‘sticks’ of the same type cross or touch each other that represents electrical contact.

19. Stick Diagrams – Some rules
Rule 2. When two or more ‘sticks’ of different type cross or touch each other there is no electrical contact. (If electrical contact is needed we have to show the connection explicitly).

20. Stick Diagrams – Some rules
Rule 3. When a poly crosses diffusion it represents a transistor.
Note: If a contact is shown then it is not a transistor.

21. Stick Diagrams – Some rules
Rule 4. In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All pMOS must lie on one side of the line and all nMOS will have to be on the other side.

22. Stick diagram -> CMOS transistor circuit
Vdd = 5V
Vout
Vdd = 5V
Vin
pMOS
Vin
Vout
nMOS
In practice, first draw stick diagram for nMOS section and analyse (pMOS is dual of nMOS section)

23. Stick Diagrams
Stick Diagrams
Gnd
VDD X
VDD
Gnd

24. Static CMOS NAND gate

25. Static CMOS NOR gate

26. Static CMOS Design Example Layout

27. Draw the stick diagram

28. Identify the Circuit

30. CMOS INVERTER

31. Layout of CMOS NAND

32. Please practice more examples

33. Design Rules

34. Design rules
Circuit engineers needs to reduce the size but process engineers needs a controllable and reproducible fabrication
So we needs design rules to get more yield.
Design rules can never be met exactly at the wafer level because physical nature of semiconductor causes some variations.
Parameter limits that cover six standard deviation
ensure that 99.7 percentage meets the specification.

35. Design Rules
Interface between the circuit designer and process engineer
Guidelines for constructing process masks
Unit dimension: minimum line width
scalable design rules: lambda parameter
absolute dimensions: micron rules
Rules constructed to ensure that design works even when small fab errors (within some tolerance) occur
A complete set includes
set of layers
intra-layer: relations between objects in the same layer
inter-layer: relations between objects on different layers

36. Why Have Design Rules?
To be able to tolerate some level of fabrication errors such as
Mask misalignment
Dust
Process parameters (e.g., lateral diffusion)
Rough surfaces
Motivation for design rules – next slide

37. l Based Design Rules Chips are specified with set of masks
Minimum dimensions of masks determine transistor size (and hence speed, cost, and power)
Feature size f = distance between source and drain
Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so
Normalize for feature size when describing design rules
Express rules in terms of l = f/2
E.g. l = 0.3 mm in 0.6 mm process
0: Introduction

38. NMOS Design Rules( based)
Minimum width of PolySi and diffusion line 2
Minimum width of Metal line 3 as metal lines run over a more uneven surface than other conducting layers to ensure their continuity
Metal
Diffusion 3 2 2
Polysilicon

39. Design Rules Metal 2 Diffusion 2 3 Polysilicon
PolySi – PolySi space 2
Metal - Metal space 2
Diffusion – Diffusion 3 To avoid the possibility of their associated regions overlapping and conducting current
Metal 2
Diffusion 2 3
Polysilicon

40. Design Rules Metal Diffusion  Polysilicon Diffusion – PolySi 
Metal lines can pass over both diffusion and polySi without electrical effect. Where no separation is specified, metal lines can overlap or cross
Metal
Diffusion 
Polysilicon

41. Metal Vs PolySi/Diffusion
Metal lines can pass over both diffusion and polySi without electrical effect
It is recommended practice to leave  between a metal edge and a polySi or diffusion line to which it is not electrically connected
Metal 
Polysilicon

42. Depletion Transistor
We need depletion implant
An implant surrounding the Transistor by 2l
Ensures that no part of the transistor remains in the enhancement mode
A separation of 2l from the gate of an
enhancement transistor avoids affecting
the device. 2l

43. Depletion Transistor
Implants are separated by 2l to prevent them from merging 2l

44. Contact Area must be a min. of 2l*2l to ensure adequate contact area.

45. Contact Cut Metal connects to polySi/diffusion by contact cut.
Contact area: 2l*2l
Metal and polySi or diffusion must overlap this contact area by l so that the two desired conductors encompass the contact area despite any mis-alignment between conducting layers and the contact hole 4l

46. Contact Cut Contact cut – any gate: 2l apart
Why? No contact to any part of the gate. 4l 2l

47. Contact Cut Contact cut – contact cut: 2l apart
Why? To prevent holes from merging. 2l

48. Nmos Design rules N+Diffusion Mask Diffusion width 2λ
Diffusion spacing 3λ
Implant Mask
Implant gate overlap 1.5λ
Implant to enhancement gate spacing 1.5λ
Buried contact mask
Buried contact to active device 2λ(to avoid short circuit)
Overlap in diffusion direction 2λ
Overlap in poly or field direction 1λ
Buried contact to unrelated poly or diffusion spacing 2λ

49. Poly Mask
Poly width 2λ
Poly spacing 2λ
Poly diffusion spacing 1λ
Poly gate extension beyond diffusion 2 λ
Diffuin to poly edge 2 λ
Contact Mask
Contact size 2 λ x 2 λ
Contact diffusion overlap 1 λ
Contact poly overlap 1 λ
Contact to contact space 2 λ
Contact to FET channel 2 λ
Contact to metal overlap 1 λ
Metal mask
Metal width 3 λ
Metal spacing 3 λ

50. Rules for CMOS layout
To ensure the separation of the PMOS and NMOS devices,
n-well supporting PMOS is 6l away from the active area of NMOS transistor.
n-well
Why?
Avoids overlap of the associated regions n+ 6l

51. Rules for CMOS layout 2l
N-well must completely surround the PMOS device’s active area by 2l

52. Rules for CMOS layout 2l
The threshold implant mask covers all n-well and surrounds the n-well by l

53. Rules for CMOS layout
The p+ diffusion mask defines the areas to receive a p+ diffusion.
It is coincident with the threshold mask surrounding the PMOS transistor but excludes the n-well region to be connected to the supply. 2l

54. Rules for CMOS layout
A p+ diffusion is required to effect the ground connection to the substrate. Thus mask also defines this substrate region. It surrounds the conducting material of this contact by l. 4

55. Simplified Design Rules
Conservative rules to get you started
0: Introduction

56. Micron rules

58. Intra-Layer Design Rule Origins
Minimum dimensions (e.g., widths) of objects on each layer to maintain that object after fab
minimum line width is set by the resolution of the patterning process (photolithography)
Minimum spaces between objects (that are not related) on the same layer to ensure they will not short after fab
0.3 micron
why would the spacing of the active (n) area be different that drawn? - due to lateral diffusion
0.15
0.3 micron
0.15

59. Intra-Layer Design Rules4
Metal2 3

60. Transistor Layout

61. Select Layer

62. Please refer the text for more details about the design rules….
Text:VLSI Technology
Author:Sujatha Pandey and Manoj Pandey
Page No.:5.36 to 5.44

63. Course Topics Introduction to CMOS circuits
MOS transistor theory, processing technology
CMOS circuit and logic design
System design methods
CAD algorithms for backend design
Case studies, CAD tools, etc.
Oct 2010

64. Bibliography Textbook Weste and Harris. CMOS VLSI Design (3rd edition)
Addison Wesley
ISBN:
Available at amazon.com.
Oct 2010

65. Introduction Integrated circuits: many transistors on one chip.
Very Large Scale Integration (VLSI): very many
Complementary Metal Oxide Semiconductor
Fast, cheap, low power transistors
Introduction: How to build your own simple CMOS chip
CMOS transistors
Building logic gates from transistors
Transistor layout and fabrication
Rest of the course: How to build a good CMOS chip
Oct 2010

66. A Brief History 1958: First integrated circuit 2003
Flip-flop using two transistors
Built by Jack Kilby at Texas Instruments
2003
Intel Pentium 4 mprocessor (55 million transistors)
512 Mbit DRAM (> 0.5 billion transistors)
53% compound annual growth rate over 45 years
No other technology has grown so fast so long
Driven by miniaturization of transistors
Smaller is cheaper, faster, lower in power!
Revolutionary effects on society
Oct 2010

67. Annual Sales 1018 transistors manufactured in 2003
100 million for every human on the planet
Oct 2010

68. Invention of the Transistor
Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable
1947: first point contact transistor
John Bardeen and Walter Brattain at Bell Labs
Read Crystal Fire
by Riordan, Hoddeson
Oct 2010

69. Transistor Types Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between source and drain
Low power allows very high integration
Oct 2010

70. MOS Integrated Circuits
1970’s processes usually had only nMOS transistors
Inexpensive, but consume power while idle
1980s-present: CMOS processes for low idle power
Intel bit SRAM
Intel bit mProc
Oct 2010

71. Moore’s Law 1965: Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale
Transistor counts have doubled every 26 months
Integration Levels
SSI: 10 gates
MSI: gates
LSI: 10,000 gates
VLSI: > 10k gates
Oct 2010

72. Oct 2010

73. Oct 2010

74. Oct 2010

75. Corollaries Many other factors grow exponentially
Ex: clock frequency, processor performance
Oct 2010

76. Silicon Lattice Transistors are built on a silicon substrate
Silicon is a Group IV material
Forms crystal lattice with bonds to four neighbors
Oct 2010

77. Dopants Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type)
Group III: missing electron, called hole (p- type)
Oct 2010

78. p-n Junctions
A junction between p-type and n-type semiconductor forms a diode.
Current flows only in one direction
Oct 2010

79. nMOS Transistor Four terminals: gate, source, drain, body
Gate – oxide – body stack looks like a capacitor
Gate and body are conductors
SiO2 (oxide) is a very good insulator
Called metal – oxide – semiconductor (MOS) capacitor
Even though gate is
no longer made of metal
Oct 2010

80. nMOS Operation Body is commonly tied to ground (0 V)
When the gate is at a low voltage:
P-type body is at low voltage
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF
Oct 2010

81. nMOS Operation Cont. When the gate is at a high voltage:
Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type
Now current can flow through n-type silicon from source through channel to drain, transistor is ON
Oct 2010

82. pMOS Transistor Similar, but doping and voltages reversed
Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
Oct 2010

83. Power Supply Voltage GND = 0 V In 1980’s, VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
Oct 2010

84. Transistors as Switches
We can view MOS transistors as electrically controlled switches
Voltage at gate controls path from source to drain
Oct 2010

85. CMOS Inverter A Y 1
Oct 2010

86. CMOS Inverter A Y 1
Oct 2010

87. CMOS Inverter A Y 1
Oct 2010

88. CMOS NAND Gate A B Y 1
Oct 2010

89. CMOS NAND Gate A B Y 1
Oct 2010

90. CMOS NAND Gate A B Y 1
Oct 2010

91. CMOS NAND Gate A B Y 1
Oct 2010

92. CMOS NAND Gate A B Y 1
Oct 2010

93. CMOS NOR Gate A B Y 1
Oct 2010

94. 3-input NAND Gate Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0
Oct 2010

95. Compound Gates Compound gates can do any inverting function Ex:
Oct 2010

96. Example: O3AI
Oct 2010

97. CMOS Fabrication CMOS transistors are fabricated on silicon wafer
Oct 2010
CMOS Fabrication
CMOS transistors are fabricated on silicon wafer
Lithography process similar to printing press
On each step, different materials are deposited or etched
Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process
Oct 2010

98. Inverter Cross-section
Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistors
Oct 2010

99. Well and Substrate Taps
Substrate must be tied to GND and n- well to VDD
Metal to lightly-doped semiconductor forms poor connection (used for Schottky Diode)
Use heavily doped well and substrate contacts / taps
Oct 2010

100. Inverter Mask Set Transistors and wires are defined by masks
Cross-section taken along dashed line
Oct 2010

101. Oct 2010

102. Detailed Mask Views Six masks n-well Polysilicon n+ diffusion
p+ diffusion
Contact
Metal
Oct 2010

103. Fabrication Steps Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
Cover wafer with protective layer of SiO2 (oxide)
Remove layer where n-well should be built
Implant or diffuse n dopants into exposed wafer
Strip off SiO2
Oct 2010

104. Oxidation Grow SiO2 on top of Si wafer
900 – 1200 C with H2O or O2 in oxidation furnace
Oct 2010

105. Photoresist Spin on photoresist
Photoresist is a light-sensitive organic polymer
Softens where exposed to light
Oct 2010

106. Lithography Expose photoresist through n-well mask
Strip off exposed photoresist
Oct 2010

107. Etch Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been exposed
Oct 2010

108. Strip Photoresist Strip off remaining photoresist
Use mixture of acids called piranha etch
Necessary so resist doesn’t melt in next step
Oct 2010

109. n-well n-well is formed with diffusion or ion implantation Diffusion
Place wafer in furnace with arsenic gas
Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO2, only enter exposed Si
Oct 2010

110. Strip Oxide Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps
Oct 2010

111. Polysilicon Deposit very thin layer of gate oxide
< 20 Å (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer
Place wafer in furnace with Silane gas (SiH4)
Forms many small crystals called polysilicon
Heavily doped to be good conductor
Oct 2010

112. Polysilicon Patterning
Use same lithography process to pattern polysilicon
Oct 2010

113. N-diffusion
Use oxide and masking to expose where n+ dopants should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-well contact
Oct 2010

114. N-diffusion (cont.)
Pattern oxide and form n+ regions
Oct 2010

115. N-diffusion (cont.) Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusion
Oct 2010

116. N-diffusion (cont.) Strip off oxide to complete patterning step
Oct 2010

117. P-Diffusion
Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact
Oct 2010

118. Contacts
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
Oct 2010

119. Metalization Sputter on copper / aluminum over whole wafer
Pattern to remove excess metal, leaving wires
Oct 2010

120. Layout Chips are specified with set of masks
Minimum dimensions of masks determine transistor size (and hence speed, cost, and power)
Feature size f = distance between source and drain
Set by minimum width of polysilicon
Feature size scales ~X0.7 every 2 years both lateral and vertical
Moore’s law
Normalize feature size when describing design rules
Express rules in terms of l = f/2
E.g. l = 0.3 mm in 0.6 mm process
Today’s l = 0.01 mm (10 nanometer = meter)
Oct 2010

121. Simplified Design Rules
Conservative rules to get you started
Oct 2010

122. Inverter Layout Transistor dimensions specified as Width / Length
Minimum size is 4l / 2l, sometimes called 1 unit
In f = 0.01 mm process, this is 0.04 mm wide, mm long
Oct 2010

123. Summary MOS Transistors are stack of gate, oxide, silicon
Can be viewed as electrically controlled switches
Build logic gates out of switches
Draw masks to specify layout of transistors
Now you know everything necessary to start designing schematics and layout for a simple circuit!
Oct 2010