1. VLSI System Design DC & Transient Response
Engr. Noshina Shamir
UET,Taxila

2. Outline DC Response Logic Levels and Noise Margins Transient Response
Delay Estimation
4: DC and Transient Response

3. Activity 1) If the width of a transistor increases, the current will
increase decrease not change 
2)     If the length of a transistor increases, the current will
increase decrease not change
3)     If the supply voltage of a chip increases, the maximum transistor current will
4)     If the width of a transistor increases, its gate capacitance will
5)     If the length of a transistor increases, its gate capacitance will
6)     If the supply voltage of a chip increases, the gate capacitance of each transistor will
4: DC and Transient Response

4. Activity 1) If the width of a transistor increases, the current will
increase decrease not change 
2)     If the length of a transistor increases, the current will
increase decrease not change
3)     If the supply voltage of a chip increases, the maximum transistor current will
4)     If the width of a transistor increases, its gate capacitance will
5)     If the length of a transistor increases, its gate capacitance will
6)     If the supply voltage of a chip increases, the gate capacitance of each transistor will
4: DC and Transient Response

5. DC Response DC Response: Vout vs. Vin for a gate Ex: Inverter
When Vin = 0 -> Vout = VDD
When Vin = VDD -> Vout = 0
In between, Vout depends on
transistor size and current
By KCL, must settle such that
Idsn = |Idsp|
We could solve equations
But graphical solution gives more insight
4: DC and Transient Response

6. Transistor Operation Current depends on region of transistor behavior
For what Vin and Vout are nMOS and pMOS in
Cutoff?
Linear?
Saturation?
4: DC and Transient Response

7. nMOS Operation Cutoff Linear Saturated Vgsn < Vgsn > Vdsn <
4: DC and Transient Response

8. nMOS Operation Cutoff Linear Saturated Vgsn < Vtn Vgsn > Vtn
Vdsn < Vgsn – Vtn
Vdsn > Vgsn – Vtn
4: DC and Transient Response

9. nMOS Operation Cutoff Linear Saturated Vgsn < Vtn Vgsn > Vtn
Vdsn < Vgsn – Vtn
Vdsn > Vgsn – Vtn
Vgsn = Vin
Vdsn = Vout
4: DC and Transient Response

10. nMOS Operation Cutoff Linear Saturated Vgsn < Vtn Vin < Vtn
Vdsn < Vgsn – Vtn
Vout < Vin - Vtn
Vdsn > Vgsn – Vtn
Vout > Vin - Vtn
Vgsn = Vin
Vdsn = Vout
4: DC and Transient Response

11. pMOS Operation Cutoff Linear Saturated Vgsp > Vgsp < Vdsp >
4: DC and Transient Response

12. pMOS Operation Cutoff Linear Saturated Vgsp > Vtp Vgsp < Vtp
Vdsp > Vgsp – Vtp
Vdsp < Vgsp – Vtp
4: DC and Transient Response

13. pMOS Operation Cutoff Linear Saturated Vgsp > Vtp Vgsp < Vtp
Vdsp > Vgsp – Vtp
Vdsp < Vgsp – Vtp
Vgsp = Vin - VDD
Vdsp = Vout - VDD
Vtp < 0
4: DC and Transient Response

14. pMOS Operation Cutoff Linear Saturated Vgsp > Vtp
Vin > VDD + Vtp
Vgsp < Vtp
Vin < VDD + Vtp
Vdsp > Vgsp – Vtp
Vout > Vin - Vtp
Vdsp < Vgsp – Vtp
Vout < Vin - Vtp
Vgsp = Vin - VDD
Vdsp = Vout - VDD
Vtp < 0
4: DC and Transient Response

15. I-V Characteristics Make pMOS is wider than nMOS such that bn = bp
4: DC and Transient Response

16. Current vs. Vout, Vin
4: DC and Transient Response

17. Load Line Analysis For a given Vin: Plot Idsn, Idsp vs. Vout
Vout must be where |currents| are equal in
4: DC and Transient Response

18. Load Line Analysis
Vin = 0
4: DC and Transient Response

19. Load Line Analysis
Vin = 0.2VDD
4: DC and Transient Response

20. Load Line Analysis
Vin = 0.4VDD
4: DC and Transient Response

21. Load Line Analysis
Vin = 0.6VDD
4: DC and Transient Response

22. Load Line Analysis
Vin = 0.8VDD
4: DC and Transient Response

23. Load Line Analysis
Vin = VDD
4: DC and Transient Response

24. Load Line Summary
4: DC and Transient Response

25. DC Transfer Curve Transcribe points onto Vin vs. Vout plot
4: DC and Transient Response

26. Operating Regions Revisit transistor operating regions Region nMOS
pMOS A B C D E
4: DC and Transient Response

27. Operating Regions Revisit transistor operating regions Region nMOS
pMOS A
Cutoff
Linear B
Saturation C D E
4: DC and Transient Response