1. Figure 1.1 The Altera UP 1 CPLD development board.

2. Figure 1.2 Design process for schematic or VHDL entry.
Compilation
Simulation
Verifcation
Graphical Entry
Timing Diagram
Program CPLD
Compiler
Timing Analysis
UP 1 Development Board
HDL Entry
Figure 1.2 Design process for schematic or VHDL entry.

3. Figure 1.3 Connections between the pushbuttons, the LEDs, and the Altera FLEX device.

4. Figure 1.4 FLEX chip pin connection to seven-segment display decimal point.

5. Figure 1.5a and 1.5b. Equivalent circuits for ORing active low inputs and outputs.

6. Figure 1.6 Active low OR-gate schematic example with pinouts.

7. Table 1.1 Hardwired connections on the FLEX chip for the design.
Device
Pin Number Connections
PB1 28
PB2 29
LED Decimal Point
On the Left
Seven-Segment Display 14

8. Figure 1.7 Active low OR-gate schematic with pin numbers assigned.

9. Figure 1.8 Compilation of active low OR-gate schematic.

10. Figure 1.9 Active low OR-gate timing simulation.
Figure 1.9 Active low OR-gate timing simulation.

11. Figure ALTERA UP 1 board with jumper settings and PB1, PB2, and LED locations.

12. Table 1.2 Jumper settings for downloading to the MAX and FLEX devices.

13. Figure 1.11 VHDL Entity declaration text.

14. Figure 1.12 VHDL OR-gate model (with syntax error).
Figure VHDL OR-gate model (with syntax error).

15. Figure 1.13 VHDL compilation with a syntax error.

16. Figure 1.14 Verilog module declaration text.

17. Figure 1.15 Verilog active low OR-gate model (with syntax error).

18. Figure 1.16 Verilog compilation with a syntax error.

19. Figure 1.17 Timing analyzer showing input to output timing delays.

20. Figure 1.18 Floorplanner with internal CPLD placement of OR-gate logic cell and I/O pins.

21. ORGATE
PB1
LED
PB2 1
Figure OR gate logic symbol.