1. Lottery
Speaker: Tsung-Yi Wu

2. Architecture
4 LEDs
STOP Switch
RESET Switch

3. How to Play Setup Play Switch RESET on Switch RESET off Guess 4 digits
Switch STOP off
Switch STOP on

4. RTL Code proc module proc (reset,clk,led,stop,inc);
input clk,reset,stop;
input[9:0] inc;
output[6:0] led;
reg[6:0] led;
reg[9:0] q;
reg[22:0] cnt;
reset or posedge clk)
if (reset) begin
cnt=0;
q=10'b ;
end
else
begin
if (stop)
cnt = cnt+inc;
if (cnt[22]==1) begin
q={q[8:0],q[9]};
cnt = 0;

5. RTL Code proc always @(q) begin led=7'b1111111;
if (q[9]==1) led=7'b ;
if (q[8]==1) led=7'b ;
if (q[7]==1) led=7'b ;
if (q[6]==1) led=7'b ;
if (q[5]==1) led=7'b ;
if (q[4]==1) led=7'b ;
if (q[3]==1) led=7'b ;
if (q[2]==1) led=7'b ;
if (q[1]==1) led=7'b ;
if (q[0]==1) led=7'b ;
end
endmodule

6. RTL Code top module top (reset,clk,led,stop,an3,an2,an1,an0);
input clk,reset,stop;
output[6:0] led;
wire[6:0] tled0,tled1,tled2,tled3,t1,t2,t3;
output an3,an2,an1,an0;
reg[10:0] cnt;
reg tmp,an3,an2,an1,an0;
assign led = (an3==0) ? tled3 : t1;
assign t1 = (an2==0) ? tled2 : t2;
assign t2 = (an1==0) ? tled1 : t3;
assign t3 = (an0==0) ? tled0 : 7'b ;

7. RTL Code top always @(posedge reset or posedge clk) if (reset) begin
an3=0;
an2=1;
an1=1;
an0=1;
end
else begin
cnt = cnt+1;
if (cnt==0) begin
tmp = an0;
an0 = an1;
an1 = an2;
an2 = an3;
an3 = tmp;

8. RTL Code top proc x0 (reset,clk,tled0,stop,10'd7);
endmodule

9. Lab Debug Write Testbench Write UCF Programming FPGA Bonus
Follow the procedures described in “How to Play” slide.
Write UCF
Programming FPGA
Bonus
Rewrite de-bouncing function

10. Appendix
Four-Digit, Seven-Segment LED Display

11. Appendix
Controlling Way