1. National Taiwan University *E-mail: mhliaoa@ntu.edu.tw
The demonstration of colossal magneto-capacitance and “negative” capacitance effect with the promising characteristics of Jg-EOT and transistor’s performance on Ge (100) n-FETs by the novel magnetic gate stack scheme design
M.-H. Liao*, S. C. Huangs, C. Y. Lius, P. G. Chens, S. C. Kaos, and C. Liens
National Taiwan University *
10: 50 am

2. Outline
Introduction
Basic concept and background knowledge for the magnetic gate stack design
Module work and development (BaTiO3 as HK; Magnetic FePt film as MG)
Device demonstration and analysis
Conclusions
Acknowledgement
10: 51 am

3. Key messages-I
Super Jg-EOT gate stack characteristics, ultra-high κ value, and the promising transistor’s performance are achieved on the Ge n-FET with the magnetic gate stack.
~75% κ-value improvement, ~100X Jg reduction, ~50% Ion enhancement, and the “negative” capacitance effect, which is important for the future steeper sub-threshold swing (S.S) device design, are demonstrated.
The high Cgate/κ-value is generated by more dipoles in the HK dielectric layer with the coupling of the built-in magnetic field from MG (Colossal magneto-capacitance).

4. Key messages-II
The novel magnetic gate stack scheme (BaTiO3 HK+ FePt MG), proposed in this work, with the super Jg-EOT characteristics, “negative” capacitance phenomenon, and the promising transistor’s performance on the high mobility (Ge) material provides the useful solution for the future low power mobile device design.

5. Outline
Introduction
Basic concept and background knowledge for the magnetic gate stack design
Module work and development (BaTiO3 as HK; Magnetic FePt film as MG)
Device demonstration and analysis
Conclusions
Acknowledgement
10: 53 am

6. Outline
Introduction
Ge device
Spin electronic device and magnetic material
Basic concept and background knowledge for the magnetic gate stack design
Module work and development (BaTiO3 as HK; Magnetic FePt film as MG)
Device demonstration and analysis
Conclusions
Acknowledgement

7. Outline
Introduction
Ge device
Spin electronic device and magnetic material
Basic concept and background knowledge for the magnetic gate stack design
Module work and development (BaTiO3 as HK; Magnetic FePt film as MG)
Device demonstration and analysis
Conclusions
Acknowledgement

8. Introduction: Ge device
One of the bottlenecks for Ge FET is the gate stack design.
Another issue is stress development, which will be discussed by our another work in T20-2 (Thursday, June 12, 1:55 p.m.).

9. Introduction: Ge device
Some research groups demonstrate ~0.7 nm EOT using HfO2/Al2O3/GeOx/Ge gate stack fabricated by plasma post oxidization. (VLSI, 2012.)

10. Introduction: Ge device
Some research groups use IL-free ZrO2 as gate stack and/or use novel ozone oxidation method to passivate the surface. (IEDM, 2012.)

11. Introduction: Ge device
Ge/GeOx/Y2O3 gate stack scheme is also studied. (VLSI, 2013.)

12. Introduction: Ge device
Oxygen potential engineering for HfO2/Al2O3/GeOx gate stack is also reported. (IEDM, 2013.)

13. Introduction: Ge device
The Jg-EOT improvement window by the continuous process optimization seems to be limited. N

14. Introduction: Ge device
The Jg-EOT improvement window by the continuous process optimization seems to be limited.
Need the new concept to form the advanced Ge gate stack.

15. Introduction: Ge device
The Jg-EOT improvement window by the continuous process optimization seems to be limited.
In this work, we propose the novel magnetic FePt as Ge MG !

16. Outline
Introduction
Ge device
Spin electronic device and magnetic material
Basic concept and background knowledge for the magnetic gate stack design
Module work and development (BaTiO3 as HK; Magnetic FePt film as MG)
Device demonstration and analysis
Conclusions
Acknowledgement

17. Introduction: Spin electronic device and magnetic material-I
Ref: IEDM 2013 short course given by Dr. Dmitri Nikonov.
Spin electronic devices with several structures are studied.
Three mechanisms demonstrate magneto-electric effect: magnetostrictive, multiferroic, and surface anisotropy.

18. Introduction: Spin electronic device and magnetic material-II (Spin FET)
Ref: IEDM 2013 short course given by Dr. Dmitri Nikonov.
Magnetic source and drain is used to spin polarized carriers.
The energy band structures for spin up/down is influenced.

19. Introduction: Spin electronic device and magnetic material-III (Magento-resistance)
Ref: IEDM 2013 short course given by Dr. Dmitri Nikonov.
Nobel Prize 2007, physics.
Magnetic source and drain is used to spin polarized carriers.
Based on the TMR theory, the DOS, tunneling rate, and current density can be controlled by the spin-directions.

20. Introduction: Spin electronic device and magnetic material-IV (Magnetic-junctions)
Ref: J. G. Alzate/UCLA in IEDM 2012.
Ref: J. T. Heron/UCB(Intel) in PRL 2001.
Switching of the nano-scale magnetic tunnel junction is also reported, which can be the application for the S/D design.
No study focus on the magnetic material as the MG so far !!

21. Introduction: Spin electronic device and magnetic material-IV (Magnetic-junctions)
Ref: J. G. Alzate/UCLA in IEDM 2012.
Ref: J. T. Heron/UCB(Intel) in PRL 2001.
Switching of the nano-scale magnetic tunnel junction is also reported, which can be the application for the S/D design.
In this work, we propose the novel magnetic FePt as Ge MG !

22. Could we use the magnetic material as the MG on the high mobility Ge FET ?
Magnetic Gate Control ?

23. Could we use the magnetic material as the MG on the high mobility Ge FET ?
In this work, we demonstrate the BaTiO3 HK + Magnetic FePt MG on Ge n-FET with the promising device behavior.
High mobility Ge FET
Magnetic Gate Control

24. Outline
Introduction
Basic concept and background knowledge for the magnetic gate stack design
Module work and development (BaTiO3 as HK; Magnetic FePt film as MG)
Device demonstration and analysis
Conclusions
Acknowledgement
10: 58 am

25. Basic concept and background knowledge for the magnetic gate stack design
Colossal magneto-capacitance effect* is used and designed to enhance the K-value/Cgate in the magnetic Ge gate stack.
* Ref: Nature, Vol. 434, p. 364 (2005)

26. Basic concept and background knowledge for the magnetic gate stack design
Colossal magneto-capacitance effect* is used and designed to enhance the K-value/Cgate in the magnetic Ge gate stack.
* Ref: Nature, Vol. 434, p. 364 (2005)

27. Basic concept and background knowledge for the magnetic gate stack design
Colossal magneto-capacitance effect* is used and designed to enhance the K-value/Cgate in the magnetic Ge gate stack.
* Ref: Nature, Vol. 434, p. 364 (2005)

28. Basic concept and background knowledge for the magnetic gate stack design
Colossal magneto-capacitance effect* is used and designed to enhance the K-value/Cgate in the magnetic Ge gate stack.
* Ref: Nature, Vol. 434, p. 364 (2005)

29. Basic concept and background knowledge for the magnetic gate stack design
Colossal magneto-capacitance effect* is used and designed to enhance the K-value/Cgate in the magnetic Ge gate stack.
* Ref: Nature, Vol. 434, p. 364 (2005)

30. Basic concept and background knowledge for the magnetic gate stack design
Colossal magneto-capacitance effect* is used and designed to enhance the K-value/Cgate in the magnetic Ge gate stack.
* Ref: Nature, Vol. 434, p. 364 (2005)

31. Basic concept and background knowledge for the magnetic gate stack design
Colossal magneto-capacitance effect* is used and designed to enhance the K-value/Cgate in the magnetic Ge gate stack.
* Ref: Nature, Vol. 434, p. 364 (2005)

32. Outline
Introduction
Basic concept and background knowledge for the magnetic gate stack design
Module work and development (BaTiO3 as HK; Magnetic FePt film as MG)
Device demonstration and analysis
Conclusions
Acknowledgement
11: 00 am

33. Outline
Introduction
Basic concept and background knowledge for the magnetic gate stack design
Module work and development (BaTiO3 as HK; Magnetic FePt film as MG)
BaTiO3 as HK
Magnetic FePt film as MG
Device demonstration and analysis
Conclusions
Acknowledgement

34. Outline
Introduction
Basic concept and background knowledge for the magnetic gate stack design
Module work and development (BaTiO3 as HK; Magnetic FePt film as MG)
BaTiO3 as HK
Magnetic FePt film as MG
Device demonstration and analysis
Conclusions
Acknowledgement

35. Module work and development : BaTiO3 as HK-I
Tetragonal (T) phase BaTiO3 is used with XRD check.
The dielectric film quality of BaTiO3 is uniform.

36. Module work and development : BaTiO3 as HK-II
Ref: Dr. Yao/Xian Jiao-tong Uni. in 2012.
BaTiO3 is processed by Pulsed Laser Deposition or Sputter.
IL-free is demonstrated by novel ozone oxidation method (IEDM, 2012.) to passivate the surface with the TEM check.

37. Outline
Introduction
Basic concept and background knowledge for the magnetic gate stack design
Module work and development (BaTiO3 as HK; Magnetic FePt film as MG)
BaTiO3 as HK
Magnetic FePt film as MG
Device demonstration and analysis
Conclusions
Acknowledgement

38. Module work and development : Magnetic FePt film as MG-I
Higher (001)/(111) intensity ratio in XRD and lower c/a ratio demonstrate the high magnetic perpendicular anisotropy in our FePt film <Process C>.

39. Module work and development : Magnetic FePt film as MG-II
Our FePt has the higher magnetic perpendicular anisotropy (~0.2T) based on the VSM measurement.
The film quality of magnetic FePt is uniform.

40. Module work and development : Magnetic FePt film as MG-III
Our FePt has the higher magnetic perpendicular anisotropy (~0.2T) based on the VSM measurement.
Our FePt film is the hard magnetic material, not soft magnetic material for the memory application.

41. Module work and development : Magnetic FePt film as MG-IV
The magnetic field is always existed in the FePt film to couple the dipoles in the HK layer and results in the higher K-value, gate stack property, and device performance.
No matter what the device is at the on-state or off-state.

42. Outline
Introduction
Basic concept and background knowledge for the magnetic gate stack design
Module work and development (BaTiO3 as HK; Magnetic FePt film as MG)
Device demonstration and analysis
Conclusions
Acknowledgement
11: 03 am

43. Outline
Introduction
Basic concept and background knowledge for the magnetic gate stack design
Module work and development (BaTiO3 as HK; Magnetic FePt film as MG)
Device demonstration and analysis
MOSCAP data
Transistor demonstration
“Negative” capacitance effect
Conclusions
Acknowledgement

44. Outline
Introduction
Basic concept and background knowledge for the magnetic gate stack design
Module work and development (BaTiO3 as HK; Magnetic FePt film as MG)
Device demonstration and analysis
MOSCAP data
Transistor demonstration
“Negative” capacitance effect
Conclusions
Acknowledgement

45. Device demonstration and analysis : MOSCAP data-I
Based on the colossal magneto-capacitance effect on our magnetic Ge gate scheme, 1.75X Cgate improvement is observed.
It is the first time to integrate the “built-in” magnetic MG in the Ge FET, operated on the room temperature.

46. Device demonstration and analysis : MOSCAP data-II
~100X Jg reduction is also observed in the magnetic MG. Root cause is still a open-question.
Leading-edge Ge gate stack characteristics is achieved with the application of the magnetic MG.

47. Device demonstration and analysis : MOSCAP data-III
~100X Jg reduction is also observed in the magnetic MG. Root cause is still a open-question.
Leading-edge Ge gate stack characteristics is achieved with the application of the magnetic MG.

48. Device demonstration and analysis : MOSCAP data-IV
Summary and comparisons with other works.
With the “built-in” magnetic field from the designed FePt MG, the K value of BaTiO3 is enhanced ~1.75X on the room temperature.
11: 04 am

49. Outline
Introduction
Basic concept and background knowledge for the magnetic gate stack design
Module work and development (BaTiO3 as HK; Magnetic FePt film as MG)
Device demonstration and analysis
MOSCAP data
Transistor demonstration
“Negative” capacitance effect
Conclusions
Acknowledgement

50. Device demonstration and analysis : Transistor demonstration
With the integration of the “built-in” magnetic FePt MG in the Ge FET, huge Ion current improvement (~50%) can be achieved through the larger Cgate.
Detailed process flow can refer to our another work in T20-2 (Will present it on Thursday, June 12, 1:55 p.m.).

51. Outline
Introduction
Basic concept and background knowledge for the magnetic gate stack design
Module work and development (BaTiO3 as HK; Magnetic FePt film as MG)
Device demonstration and analysis
MOSCAP data
Transistor demonstration
“Negative” capacitance effect
Conclusions
Acknowledgement
11: 05 am

52. Device demonstration and analysis : “Negative” capacitance effect
SS=JVg/J(log Id)=(JVg/Jys)x(Jys/Jlog Id)=(1+Cs/Cinv)xkT/q*ln(10)
Body factor (m) is extracted from the equation SS=m x kT/q*ln(10) by the low temperature measurement, where m is defined by m=dVG/dφ. m n

53. Device demonstration and analysis : “Negative” capacitance effect
The characteristics of SS-EOT on our device is promising.
Body factor (m) is extracted from the equation SS=m x kT/q*ln(10) by the low temperature measurement, where m is defined by m=dVG/dφ.

54. Device demonstration and analysis : “Negative” capacitance effect
SS=JVg/J(log Id)=(JVg/Jys)x(Jys/Jlog Id)=(1+Cs/Cinv)xkT/q*ln(10)
Body factor (m) is extracted from the equation SS=m x kT/q*ln(10) by the low temperature measurement, where m is defined by m=JVg/Jys.

55. Device demonstration and analysis : “Negative” capacitance effect
SS=JVg/J(log Id)=(JVg/Jys)x(Jys/Jlog Id)=(1+Cs/Cinv)xkT/q*ln(10)
The “Negative” capacitance effect is also observed in our device. The reason could be due to the “dipoles” in the BaTiO3 dielectric HK layer. *[Ref: Dr. H. W. Then/intel in IEDM 2013]

56. The model for “Negative” capacitance effect
1/C=1/C1+1/C2+1/C3 MG
m-FePt
Negative - - - - - - C1
C’1
BaTiO3
BaTiO3 + + + + + + C2 C2 Ge Ge C3 C3
Ref: Dr. H. W. Then/intel in IEDM 2013
The magnetic field triggers more dipoles in the BaTiO3 layer and it results in the larger Cgate and better S.S. (m<1)
The dipoles result in the “built-in” electrical field and “mathematically negative capacitance” effect in the HK layer.

57. The model for “Negative” capacitance effect
1/C=1/C1+1/C2+1/C3 MG
m-FePt
Negative - - - - - - C1
C’1
BaTiO3
BaTiO3 + + + + + + C2 C2 Ge Ge C3 C3
The forward sweep and reverse sweep on the Id-Vg and C-V has also been checked for the “Negative capacitance effect”.
No obvious hysteresis effect is observed. It could be due to the fixed dipole’s directions under the strong magnetic field controlled by the hard magnetic FePt MG film.

58. Outline
Introduction
Basic concept and background knowledge for the magnetic gate stack design
Module work and development (BaTiO3 as HK; Magnetic FePt film as MG)
Device demonstration and analysis
Conclusions
Acknowledgement
11: 07 am

59. Conclusions-I
T-phase BaTiO3 HK layer + magnetic FePt MG film is proposed to be the gate scheme on the Ge FET.
The ~75% κ-value improvement, ~100X Jg reduction, and ~50% Ion enhancement are achieved due to the colossal magneto-capacitance effect.
The magnetic field from the magnetic FePt MG film couples and triggers the more dipoles in the BaTiO3 dielectric layer and then results in the super Cgate and κ-value successfully.

60. Conclusions-II
The “negative” capacitance effect (m<1), which is important for the future steeper S.S device design, is also observed in this work.
Super Jg-EOT characteristics, “negative” capacitance phenomenon, and the promising transistor’s performance on the high mobility (Ge) material provides the useful solution for the future low power mobile device design.

61. Outline
Introduction
Basic concept and background knowledge for the magnetic gate stack design
Module work and development (BaTiO3 as HK; Magnetic FePt film as MG)
Device demonstration and analysis
Conclusions
Acknowledgement
11: 08 am

62. Acknowledgement This work is supported by:
National Taiwan University, Taiwan, under the grant 103R7734.
Ministry of Science and Technology, Taiwan, under the grants E and E MY3.
Ministry of Economic Affairs (MEA), Taiwan, under the grant 101-EC-17-A-01-S1-219.
TSMC, Taiwan, JDP and Big League program, under the grant E

63. Back-Up
Thank a lot
11: 09 am

64. Why BTO as the HK layer ? The intrinsic K value (~178) is high.
The dipole’s sensitivity to the magnetic field is good enough.
The dipole density in BTO is higher than HfO2/Al203 from the review on the literature.
It is easy for the process.
Jg level is low…

65. This effect can work in the HfO2 case ?
Based on our experimental data, there have ~23% K-value improvement in the magnetic FePt MG+HfO2 HK device.
The less K-value improvement in the HfO2 HK device is due to the intrinsic dipole density and the dipole’s sensitivity to magnetic field in the HfO2 HK.
The transistor device process for the magnetic FePt MG+HfO2 HK is still on-going.

66. Our magnetic FePt material property?
The magnetic field in our FePt film is ~0.2T.
Our FePt film is the hard magnetic material, not soft magnetic material for the memory application.
The magnetic field is always existed to couple the dipoles in the HK layer and results in the high K value, gate stack property, and device performance. No matter the device is for the on-state or off-state.

67. FePt/BTO electrical property
The band-gap of BTO is 9.7 eV.
The DEc of BTO and Ge is 3.4 eV.
The work function of FePt MG is 4.5 eV.
0.6
4.5 4
10.3

68. Thermal budget ?
Based on our experimental data (the Vfb in the MOSCAP and Vt in the transistor), the magnetic FePt MG+BTO HK gate scheme on Ge FET can endure the ~650oC, 30mins thermal budget.
Note that the thermal budget in the designed Ge transistor full process is intrinsically lower than Si transistor device, due to the material property.
Gate Last process is the option.

69. Vt position ?
Based on the plot of Id-Vg, the Vt position is almost the same with the implement of the magnetic FePt MG film.
Magnetic FePt film is just one of the layers in the MG scheme.
The Vt position can be controlled by other layers in the MG scheme.

70. Dit level ?
The Dit level in our BTO system is about 6e11, based on the C-V measurement.

71. Dipoles density ?
The dipole density is dependent on the magnetic field.
The dipole density is still under investigation with other measured technique.
When we have the accurate number, we will update them soon……

72. Why we demonstrated it on n-FET ?
Based on the principle on magnetic FePt MG, both n- and p-FET can get the benefit from the better K-value, gate capacitance, and gate property.
The reason why we demonstrate this scheme on Ge n-FET is because, Ge n-FET device is more challenge than p-FET.
Many different groups have demonstrate high performance Ge p-FET. However, few good data on Ge n-FET is reported.

73. Our device m<1 but S.S still higher than 60 mV/dec?
The m value (=0.4 < 1) shows the possibility for the device to achieve steeper S.S. (< 60 mV/dec).
Still have many issues for the S.S. (< 60 mV/dec) demonstration at the room temperature.

74. Colossal magneto-capacitance effect and/or Negative capacitance effect?
The trigger of dipoles from magnetic field from MG
Magneto-capacitance effect
The “mathematically negative capacitance” effect
~75% Cgate improvement
Better S.S.

75. The model for “Negative” capacitance effect
1/C=1/C1+1/C2 Ge
BaTiO3 MG
m-FePt C1 C2 - +
Negative
C’1
Ref: Dr. H. W. Then/intel in IEDM 2013
The “mathematically negative capacitance” effect is observed successfully in the “built-in” magnetic device.
The magnetic field triggers more dipoles in the BaTiO3 layers and results in larger Cgate and better S.S. from increased Vg.