Dipartimento di Ingegneria e Scienze Applicate

Dipartimento di Ingegneria e Scienze Applicate
ciao Radiation- tolerant front-end electronics: from the AToM chip to 65 nm CMOS Valerio Re INFN Sezione di Pavia Università di Bergamo Dipartimento di Ingegneria e Scienze Applicate saluti

The art of low-noise front-end electronics and the problem of radiation tolerance in the work of Franco “The obvious trend towards a higher luminosity in the beams of the accelerators and higher intensities in the sources of synchrotron radiation will bring about more serious problems in the domain of radiation effects and radiation hardness of materials and devices. As already observed, this is going to be an extremely challenging area” (F. Manfredi, Considerations on the 11th European Symposium on Semiconductor Detectors, NIM A, 2010) In the course of three decades, since 1980’s, rad-hard front-end electronics for silicon detectors in particle physics experiments has been based on technology and design choices, following the evolution of microelectronic processes Franco Manfredi gave an essential contribution to the understanding of radiation effects on the noise performance of front-end devices and to the development of techniques enabling readout electronics to operate with a large signal-to-noise ratio at high radiation levels

JFETs as rad-hard devices
As a device based on the drift of majority carriers in the silicon bulk, the JFET has an intrinsically high degree of tolerance to ionizing radiation, which mostly affects silicon dioxide regions (or other dielectrics). Old CMOS technologies, with a thick gate oxide, were extremely sensitive to ionizing radiation (even at a few tens of a krad). Franco was proactive in the development of monolithic technologies based on the JFET as a low-noise, rad-hard device, addressing the radiation tolerance requirements of strip detector front-end electronics at LEP and then at LHC

JFETs as rad-hard devices: the LEP environment
“The JFET as input device in the preamplifier has over a CMOS transistor the advantage of a smaller spectral power density in the 1/f term of the series noise source…Radiation degrades the noise performance of a JFET to a lesser extent than it does for a MOSFET”. (F. Manfredi et al, On the design of a JFET-CMOS front-end for low noise data acquisition from microstrip detectors, NIM A, 1988) CMOS-compatible JFET in the Fraunhofer IMS Duisburg technology

JFETs as rad-hard devices: the LEP environment
“It became clear that long lasting design criteria had to ensure a sufficient degree of radiation tolerance….The analysis of radiation effects…leads to the decision of using the NJFET at the preamplifier input and for all functions where a low 1/f noise is required. P-channel MOSFETs are adopted as complementary elements for the N-channel JFET.” (F. Manfredi et al, Evolution in the criteria that underlie the design of a monolithic preamplifier system for microstrip detectors, NIM A, 1990)

JFETs as rad-hard devices: the LHC environment
“Experiments at new high luminosity colliders (SSC, LHC) set most severe constraints both on operating speed and radiation tolerance of the analog processors. Different steps had to be taken, in order to extend the JFET-CMOS technology, which is intrinsically radiation hard, to front-end systems for these environments” (F. Manfredi et al, JFET-CMOS process to meet the requirements of tracking applications at short processing times, NIM A, 1994)

Noise in irradiated JFETs
“After irradiation, two Lorentzian noise terms appear. The white noise, which still dominates at high frequencies, does not show any appreciable degradation” (F. Manfredi et al, JFET-CMOS process to meet the requirements of tracking applications at short processing times, NIM A, 1994) “The characteristic frequencies of Lorentzian noise … occur at much lower (values) in the P-channel than in the N-channel device. Although the P device has a larger channel thermal noise before and after irradiation, there is a broad frequency range where the irradiated P-device features less noise than the irradiated N-device” (F. Manfredi et al, “Trends in the design of front-end systems for room temperature solid state detectors”, IEEE TNS, 2004) Before irradiation 1 Mrad TID, 60Co g-rays

Rad-hard CMOS In the 90’s, high density front-end integrated circuits were required for the readout of high granularity silicon vertex detectors (microstrips, and then pixels), with readout channels. The integration of the analog front-end with high performance digital circuits for sparsified readout, data storage and transmission was made possible by CMOS technology scaling to the submicron region. Special rad-hard CMOS processes were very interesting in view of the design of readout electronics for collider experiments with increasing luminosity. Rad-hard CMOS was based on a combination of process and layout techniques, among which: Increased NMOS threshold voltage to account for radiation-induced shifts Increased isolation spacing between NMOSFETs to prevent TID induced leakage Guard band diffusions around n-wells ….

The BaBar SVT and the AToM chip
The Honeywell 0.8 µm bulk CMOS process was selected for the CMOS readout integrated circuit for the Silicon Vertex Tracker of the BaBAR experiment at SLAC. From May 1999 the rad-hard AToM chip operated with the Silicon Vertex Tracker in the BaBar experiment at the collider PEP-II (SLAC). The SVT consisted of 5 layers of double-sided AC coupled microstrip detectors surrounding the IP and distributed at radii ranging from 3.3 cm to 14 cm. The charge collected on the strips was read out by 150,000 channel of front-end electronics mounted at both sides of the detector modules.

AToM: 128-channel CMOS IC Two versions:
It retains the analog information of the charge induced on the detector electrodes low noise amplification and shaping (selectable gain and peaking time, operation on both detector signal polarities) It has been designed for a real random operation, without any external synchronization It can simultanueously acquire and process the incoming analog signals and build up and serially transmit derandomized streams of data relevant to previous events The A/D conversion is based on the Time-over-Threshold technique polarity selection (connection to detector n-side and p-side) Charge sensitivity: 100 mV/fC (radsoft) Gain selection (150 mV/fC mV/fC) (radhard) Peaking time selection ( ns) Low power: 4mW/channel 1.5 mW/channel in the analog section chip size: 5.7x8.3mm ( devices) radiation damage: < 1Mrad (radhard) Two versions: in radiation soft technology (HP CMOS26G 0.8 µm) in radiation hard technology (required to stand 1 Mrad TID) (Honeywell RICMOS IV 0.8 µm bulk CMOS)

Time-over-Threshold (ToT) approach to analog-to-pulse width conversion
with a compression-type characteristic A very interesting study by Franco et al about the effect of electronic noise on the measurement of the Time Over Threshold: “Noise limits in a front-end system based on time-over-threshold signal processing”, NIM A439,2000 “The noise analysis has provided an insight into the behavior of a ToT processor as compared to a conventional linear processor. The ToT principle is proven to yield a viable approach to the realization of a charge measuring system with range-compression features”

Simplified diagram of the analog signal processing channel in the AToM chip

Charge-sensitive preamplifier in the AToM chip
The front-end element M13 is a PMOSFET with a gate width of 2500 µm and a gate length of 1.2 µm. The current through it is about 250 µA. At this current M13 features a transconductance above 3 mS. The size of M13 is chosen in order to work, with an acceptable mismatch, at detector capacitances ranging from 10 pF in the case of the shortest strips to about 35 pF in the case of the longest ones.

Irradiation with 60Co g-rays
AToM rad-soft Irradiation with 60Co g-rays Suitable degree of radiation tolerance in applications where radiation levels are much lower than in high energy physics experiments at colliders

after irradiation with 60Co -rays High gain setting, n-side
AToM rad-hard ENC variation at CD = 12 pF after irradiation with 60Co -rays High gain setting, n-side

Evolution of CMOS technologies and increasing demands on detector granularity, readout speed and radiation hardness The result of a shorter gate and a thinner gate oxide is a remarkable improvement in noise and radiation hardness features of the CMOS processes such as to make them fully adequate for front-end design” P.F. Manfredi et al, “Trends in the design of front-end systems for room temperature solid state detectors”, IEEE TNS, 2004 PMOSFETs from three different CMOS generations

CMOS scaling and radiation tolerance
Most of rad-hard CMOS technologies required an increased process complexity and degraded circuit performance and density relative to commercial bulk CMOS. Scaling of CMOS technologies brought along an increased level of radiation hardness, thanks to gate oxide thinning: in thin oxides (few nm) radiation-induced positive charge is removed by tunneling. Lateral isolation oxides were (and are) still thick and radiation-soft, but this can be cured in NMOSFETs by using enclosed layout transistors. This evolution led to the widespread and very successful adoption of the quarter micron CMOS node for HEP experiments at LHC and elsewhere

The FSSR2 chip Front-End Core Logic Programming Data output Interface
The analog front-end of the 128-channel FSSR2 chip can be seen as a a kind of adaptation of the AToM chip front-end to 0.25 µm CMOS. This chip was originally designed for the readout of silicon strip detectors in the BTeV experiment. It is currently used in a beam test facility at Fermilab and for the readout of strip detectors in the CLAS12 experiment at Jefferson Lab. Franco played an essential role in establishing the Fermilab – INFN Pavia collaboration that designed this chip. Data output Interface Programming Core Logic Front-End 7.5 mm x 5 mm, input pads with 50 µm pitch

FSSR2 analog channels Preamplifier Programmable Gain
To 3-bit Flash ADC Cf1 Programmable Baseline Restorer Cf Bias Hit/NoHit Discriminator + Shaper Threshold circuit Gf Comparator CD Kill BLR Single-ended/ Differential conversion - - CR-(RC)2 Vth + CAC Cinj Test Input (from Internal Pulser) Programmable Peaking time Threshold DAC (chip wide)

Charge sensitivity at shaper output:
Shaper and BLR response Charge sensitivity at shaper output: Low gain: 120 mV/fC High gain: 160 mV/fC

However, ENC is well below the spec value of 1000 e rms at CD = 20 pF.
Equivalent Noise Charge The BLR improves the threshold dispersion (AC coupling), but increases noise However, ENC is well below the spec value of 1000 e rms at CD = 20 pF.

Radiation tolerance FSSR prototype FSSR2
Irradiation with 27 MeV protons to a 1.9x1013 cm-2 fluence, corresponding to a total ionizing dose of 5 MRad After irradiation the chip remains fully functional with very little (< 10 %) degradation of critical parameters such as ENC and threshold dispersion FSSR2 Irradiation with 60Co g-rays to a total ionizing dose of 20 Mrad (no bias applied during irradiation) Chip fully functional after irradiation; noise and charge sensitivity are not affected Threshold dispersion with BLR selected increases by about 15 % (remains below the spec value of 500 e rms)

Nanoscale CMOS and rad-hard front-end chips for silicon pixel sensors
The development of small pitch pixel detectors operating at extremely high data rates and radiation levels and the enhanced performance of digital circuits led our community towards nanoscale CMOS technologies. Today the focus is on the 65 nm CMOS node for the readout of pixels at the High Luminosity LHC and at the next generation of light sources (FEL). Front-end electronics has to retain excellent noise performance after the exposure to extremely high radiation levels Digital figures of merit (speed, density, power dissipation) are driving the evolution of CMOS technologies. For analog applications in which speed and density are important, scaling can be in principle beneficial, but what about critical performance parameters such as noise, gain, radiation hardness…? In very aggressive low-power designs, small pixel cells (≤ 50 µm x 50 µm) can contain just a reduced (“shaperless”) version of the analog front-end

General schematics of a pixel analog front-end in 65 nm CMOS
Threshold adjustment by DAC or autozero; amplitude information by ToT or Flash ADC Circuit for charge restoration on the feedback capacitor C F SENSOR SHAPER DISCRIMINATOR . C Q d D ToT clock transmitted by the chip periphery, or generated by a locally triggered oscillator Vth PREAMPLIFIER Vth PA forward stage: high gain, low noise Trend is to skip the shaping stage in the RD 53 HL-LHC pixel cell, mostly because of power constraints (noise filtering in the preamplifier, or correlated double sampling at the discriminator input ) Charge restoration: handle sensor leakage current after extreme irradiation levels (max. 20 nA at 2x1016 n/cm2)

How the analog channel may look like in a HL-LHC pixel readout
INFN-Pavia IK/2 vout CD Itr=Gm vout CF Ith VREF IDAC IK 5 bit ToT counter Single amplification stage for minimum power dissipation Krummenacher feedback to comply with the expected large increase in the detector leakage current High speed, low power current comparator Relatively slow ToT clock – 80 MHz 5 bit counter – 400 ns maximum time over threshold 30000 electron maximum input charge, ~450 mV preamplifier output dynamic range Selectable gain and recovery current

CMOS generations from 250 nm to 65 nm
ciao Noise in NMOS: CMOS generations from 250 nm to 65 nm 1/f noise has approximately the same magnitude (for a same WLCOX) across different CMOS generations. White noise has also very similar properties (weak/moderate inversion). 1/f noise kf 1/f noise parameter αf 1/f noise slope-related coefficient Channel thermal noise kB Boltzmann’s constant T absolute temperature αw excess noise coefficient γ channel thermal noise coefficient In weak inversion: saluti

ciao 1/f noise: NMOS vs PMOS In bulk CMOS, the fact that PMOSFETs feature a smaller 1/f noise with respect to equally sized NMOSFETs was generally related to buried channel conduction. In deep submicron processes, it was expected that the PMOS would behave as a surface channel device, rather than a buried channel one as in older CMOS generations. With an inversion layer closer to the oxide interface, 1/f noise is expected to increase. Ultimately, PMOSFETs should feature the same 1/f noise properties as NMOSFETs. However, this was not observed in CMOS generations down to 130 nm and 90 nm. A possible interpretation can be related to the different interaction of electrons (NMOS) and holes (PMOS) with traps in the gate dielectric (different barrier energies experienced by holes and electrons across the Si/SiO2 interface) . saluti

ciao 65 nm LP process: 1/f noise In the 65 nm LP process by Foundry B, NMOS and PMOS have similar 1/f noise (especially longer transistors). This could be explained by a “surface channel” behavior for both devices, and/or by the fact that the gate dielectric nitridation decreases the barrier energy experienced by holes across the silicon-dielectric interface. This would make it easier for the PMOS channel to exchange charges with oxide traps. saluti

65 nm CMOS at extreme radiation levels
At the HL-LHC design luminosity, for an operational lifetime of 10 years, the innermost pixel layer will be exposed to a total ionizing dose of 1 Grad, and to an equivalent fluence of 1-MeV neutrons of 2 x 1016 n/cm2. If unacceptable degradation, a replacement strategy must be applied for inner pixel layers. Nanoscale CMOS (with very thin gate oxide) has a large intrinsic degree of tolerance to ionizing radiation: what happens at 1 Grad? The RD53 Radiation working group did an excellent job in studying and understanding damabge mechanisms in irradiated 65 nm CMOS transistors

Radiation effects associated with STI oxides
ciao Radiation effects associated with STI oxides TID induced positive charge gate STI Wlat,finger tOX,lat,max tOX,lat,min θ TID induced positive charge P-type substrate TID induced positive charge gate P-type Substrate (Well) STI STI STI Initially, with increasing dose a portion of the STI sidewall gets inverted because of radiation induced positive charge trapped in STI oxides. Lateral parasitic transistors are turned on and contribute to the total noise of the device. At higher doses, negative charge trapped at interface states compensates positive oxide charge, and then may even become dominant. Lateral parasitic transistors are gradually switched off as TID increases further. Their noise contribution disappears. Main transistor finger Source Drain Gate Lateral parasitic devices saluti

Radiation effects associated with STI oxides
ciao Radiation effects associated with STI oxides TID induced positive charge gate STI Wlat,finger tOX,lat,max tOX,lat,min θ TID induced positive charge P-type substrate TID induced positive charge gate P-type Substrate (Well) STI STI STI Inverted region at STI sidewall Initially, with increasing dose a portion of the STI sidewall gets inverted because of radiation induced positive charge trapped in STI oxides. Lateral parasitic transistors are turned on and contribute to the total noise of the device. At higher doses, negative charge trapped at interface states compensates positive oxide charge, and then may even become dominant. Lateral parasitic transistors are gradually switched off as TID increases further. Their noise contribution disappears. Main transistor finger Source Drain Gate Lateral parasitic devices saluti

Radiation effects associated with STI oxides negative charge trapping
ciao Radiation effects associated with STI oxides TID induced positive charge gate STI Wlat,finger tOX,lat,max tOX,lat,min θ TID induced positive charge P-type substrate TID induced positive charge gate P-type Substrate (Well) STI STI STI Inverted region at STI sidewall TID induced Interface states, negative charge trapping Initially, with increasing dose a portion of the STI sidewall gets inverted because of radiation induced positive charge trapped in STI oxides. Lateral parasitic transistors are turned on and contribute to the total noise of the device. At higher doses, negative charge trapped at interface states compensates positive oxide charge, and then may even become dominant. Lateral parasitic transistors are gradually switched off as TID increases further. Their noise contribution disappears. Main transistor finger Source Drain Gate Lateral parasitic devices saluti

Radiation effects associated with STI oxides negative charge trapping
ciao Radiation effects associated with STI oxides TID induced positive charge gate STI Wlat,finger tOX,lat,max tOX,lat,min θ TID induced positive charge P-type substrate TID induced positive charge gate P-type Substrate (Well) STI STI STI TID induced Interface states, negative charge trapping Initially, with increasing dose a portion of the STI sidewall gets inverted because of radiation induced positive charge trapped in STI oxides. Lateral parasitic transistors are turned on and contribute to the total noise of the device. At higher doses, negative charge trapped at interface states compensates positive oxide charge, and then may even become dominant. Lateral parasitic transistors are gradually switched off as TID increases further. Their noise contribution disappears. Main transistor finger Source Drain Gate Lateral parasitic devices saluti

NMOSFETs – ID variation
No sizable effects can be seen in ID vs VGS static characteristics for devices with large W/L, except in the leakage current region. But looking at these data in more detail, it is possible to see interesting effects that may be correlated with the behavior of noise in irradiated devices. At low TID, positive charge in STI oxides switches on lateral devices, increasing ID (for the same VGS) At higher doses, negative charge trapped in interface states at the STI oxides gradually compensates oxide-trapped positive charge, switching off lateral parasitic transistors and reducing ID (for the same VGS)

Total ionizing dose effects on noise in LP 65 nm CMOS
Noise is a crucial parameter for the performance of the analog front-end (affects minimum threshold setting in particle tracking applications, single photon resolution in X-ray imaging) The study of total dose effects on the noise of CMOS transistors can be an effective tool to understand radiation damage mechanisms As an example, we developed a model for the contribution of lateral parasitic transistors to the total noise of an irradiated NMOS White noise 1/f noise

NMOSFETs TSMC LP 65 nm technology – 10 Mrad
Low drain current density High drain current density Moderate 1/f noise increase at low current density, due to the contribution of lateral parasitic devices At higher currents the degradation is almost negligible because the impact of the parasitic lateral devices on the overall drain current is smaller No increase in the white noise region is detected

NMOSFETs – up to 600 Mrad Low current density
At high TID, the noise increase is not dependent on the current density, as it is instead at 10 Mrad At 200 Mrad (and even 600 Mrad), at low ID 1/f noise increase with respect to pre-irradiation values is smaller than at 10 Mrad This can be correlated with the evolution of radiation effects at increasing TID and with the behavior of ID vs VGS

NMOSFETs – 1/f noise coefficient
The effect of 1/f noise degradation can be nonnegligible. The dependence of 1/f noise increase on the drain current density is apparent at 10 Mrad. At 600 Mrad, the 1/f noise coefficient increases by about a factor of 3. At low ID, 1/f noise degradation is more severe at 10 Mrad (increase by almost a factor of 5) than at TID beyond 100 Mrad A possible explanation of this behavior is that at very high doses negative charge trapped in interface states at the STI oxides gradually compensates oxide-trapped positive charge, switching off lateral parasitic transistors At high TID noise contributions by these parasitic devices become less important; 1/f noise increase from 200 Mrad to 600 Mrad can be explained by other effects (increase of border traps in gate oxides, defects in spacer dielectrics…)

1/f noise in irradiated PMOSFETs
Again no effect is detected in the white noise region, while 1/f noise moderately increases. Lateral parasitic devices do not play a role here (positive charge is accumulated both in oxides and at interface states), so there is no dependence on the drain current density 1/f noise increase is smaller than in NMOSFETs: at 600 Mrad the 1/f noise coefficient increases by about a factor 2 (40% increase of the contribution to the ENC of a detector readout channel)

ciao Ionizing radiation effects on the signal-to-noise ratio in a pixel readout channel Noise voltage spectrum of NMOS,W/L = 5/0.13, before irradiation and at 600 Mrad TID, calculated using data from measurements The noise data reported here can provide the basis to estimate the performance of an analog front-end for pixel detectors at extremely high TID Even at a signal peaking time of 25 ns, radiation-induced 1/f noise increase has an effect in the bandwidth of an analog channel (input transistor operates at very small ID, in the low current density region) Using realistic parameters for 65nm CMOS pixel front-end prototypes developed in the frame of RD53, a % ENC increase (from 120 to 140 e rms at 100 fF CD) can be predicted, which is consistent with measurements on irradiated chips Transfer function of a shaperless front-end with 25 ns peaking time superimposed to the spectra saluti

ciao Ionizing radiation effects on the signal-to-noise ratio in a pixel readout channel The noise data reported here can provide the basis to estimate the performance of an analog front-end for pixel detectors at extremely high TID Even at a signal peaking time of 25 ns, radiation-induced 1/f noise increase has an effect in the bandwidth of an analog channel (input transistor operates at very small ID, in the low current density region) Using realistic parameters for 65nm CMOS pixel front-end prototypes developed in the frame of RD53, a % ENC increase (from 120 to 140 e rms at 100 fF CD) can be predicted, which is consistent with measurements on irradiated chips saluti

ciao Conclusions During his scientific career Franco has oriented his research interests to radiation detectors, detector signal processing, noise limits in electron devices and front-end electronics for different detector applications. He has led several international projects in the area of low-level, low-noise front-end systems for the acquisition and processing of signals from radiation detectors in nuclear and elementary particle physics (CERN, IHEP, Fermilab, SLAC, LBNL,...) Most of his work was motivated by his belief that front-end electronics developments are among the main forces responsible for the progress in physics saluti

Franco’s work is of central importance to the field of detector readout electronics, and is fundamental in understanding noise, detector matching to front-end amplifier, signal shaping and filtering, radiation effects in analog front-end circuits His work will always be an indispensable reference for future developments of low-noise, rad-hard readout electronics Franco’s work was essential for “disseminating among the community “… a number of instrumentation solutions that have been developed with the aim of making the…applications of solid-state detectors as effective as possible” (E. Gatti, P.F. Manfredi, La rivista del Nuovo Cimento 1986)

ciao Backup slides saluti

+ CD Cf Gf Shaper Preamplifier Bias BLR CAC Cinj Cf1 Programmable Peaking time Programmable Baseline Restorer Test Input - Programmable Gain CR-(RC)2 Comparator Threshold circuit Flash ADC Discriminator 2 Single-ended/ Differential conversion DAC Vth Discriminator 1 Discriminator 0

FSSR2 block diagram FSSR2 Core 128 analog channels
16 sets of logic, each handling 8 channels Core logic with BCO counter (time stamp) Programming Interface (slow control) Programmable registers DACs Data Output Interface Communicates with core logic Formats data output Same as BTeV FPIX2 chip

Advanced pixel detectors and readout microelectronics
Particle tracking at LHC- Phase II: Very high hit rates (1-2 GHz/cm2), need of an intelligent pixel-level data processing Very high radiation levels (1 Grad Total Ionizing Dose, 1016 neutrons/cm2) Small pixel cells to increase resolution and reduce occupancy (~50x50µm2 or 25x100 µm2)  Large chips: > 2cm x 2cm, ½ - 1 Billion transistors X-ray imaging at free electron laser facilities (next generation): Reduction of pixel size (100x100 mm2 or even less), presently limited by the need of complex electronic functions in the pixel cell: Large memory capacity to store images (at XFEL, ideally, 2700 frames at 4.5 MHz every 100 ms) Advanced pixel-level processing (1 – photons dynamic range, 10-bit ADC, 5 MHz operation)

RD53: an ATLAS-CMS-LCD collaboration
RD53 was organized to tackle the extreme and diverse challenges associated with the design of pixel readout chips for the innermost layers of particle trackers at future high energy physics experiments (LHC – phase II upgrade of ATLAS and CMS, CLIC) A 50 µm x 50 µm mixed-signal pixel cell readout for the phase II upgrade of LHC in 65 nm CMOS 65 nm CMOS is the candidate technology to address the requirements of these applications. It has to be fully studied and qualified in view of the design of these chips. ATLAS: CERN, Bonn, CPPM, LBNL, LPNHE Paris, Milano, NIKHEF, New Mexico, Prague, RAL, UC Santa Cruz. CMS: Bari, Bergamo-Pavia, CERN, Fermilab, Padova, Perugia, Pisa, PSI, RAL, Sevilla, Torino. Collaborators: ~100, ~50% chip designers

RD53 chip architecture 95% digital (as for FEI4)
Charge digitization (TOT or ADC) ~256k pixel channels per chip Pixel regions with buffering Data compression in End Of Column Chip size: >20 x 20 mm2

Specifications for threshold setting, noise, power, speed in the ATLAS/CMS RD53 pixel analog front-end Need of detecting charge released by MIPs in heavily damaged sensors (4000 e-) at extreme irradiation levels without efficiency degradation Threshold setting for higher tolerable noise occupancy: Qth,min = 1000 e- ENC < 150 e rms at CD = 100 fF (mostly determined by series noise, ENC is proportional to CD) Threshold dispersion after local tuning: sQth < 40 e rms (includes contributions by discriminator threshold mismatch and pixel-to-pixel preamplifier gain variations) These specifications are based on the so called 4s rule (empirical): Qth, min > 4.ENC + 4. sQth. They have to be achieved by analog circuits integrated in a small silicon area and operating at very low power: Maximum power dissipation: 6 µW/pixel (50 µm x 50 µm, or 25 µm x 100 µm) Maximum Hit time resolution = 25 ns, A/D conversion time < 400 ns

CMOS generations from 250 nm to 90 nm
ciao 1/f noise in PMOS: CMOS generations from 250 nm to 90 nm 1/f noise appears to increase (for a same WLCOX) with CMOS scaling saluti

NMOS and PMOS in an FD-SOI technology
ciao NMOS and PMOS in an FD-SOI technology We previously found that NMOS and PMOS have the same 1/f noise only in one case, that is, in fully-depleted 180 nm CMOS SOI transistors. A possible explanation was that in a very thin silicon film (40 nm) conduction takes place very close to the Si-SiO2 interface. saluti

ciao 1/f noise: NMOS vs PMOS In bulk CMOS processes close to the 100 nm threshold, the PMOS still has a lower 1/f noise than the NMOS. However, this difference tends to decrease with newer CMOS generations. saluti

Thermal noise and CMOS scaling
The origin of thermal noise can be traced to the random thermal motion of carriers in the device channel. When the MOSFET is biased in saturation (VDS > VDS,sat), the following equation can be used for the power spectral density of thermal noise in all inversion conditions: kB = Boltzmann’s constant T = absolute temperature γ = channel thermal noise coefficient (depends on inversion region; varies with the inversion layer charge: = 1/2 in weak inversion, = 2/3 in strong inversion) αw = excess noise coefficient (n = 1 – 1.5; proportional to the inverse of the slope of the ID-VGS curve in the subthreshold region)

Excess thermal noise coefficient
aW = 1 for long-channel devices. Short-channel devices can be noisier (aW > 1 ) mainly because of two effects related to high longitudinal electric fields (E = VDS/L) in the channel. Reduction of charge carrier mobility: at increasing field strength the carrier velocity is saturated at vsat=0EC (0 low-field mobility, EC critical field strength) Increase of charge carrier temperature: at increasing field strength the temperature Te of carriers in the channel increases with respect to the temperature T of the device lattice

Excess thermal noise coefficient
In saturation, the longitudinal electric field is E = (VGS – VTH)/L. It can be shown that short-channel phenomena affect thermal noise only if the value of the ratio E/EC is not negligible, which does not happen if the device is biased in weak/moderate inversion. 350 nm CMOS

1/f noise from 350 nm to 65 nm NMOS
ciao 1/f noise from 350 nm to 65 nm NMOS The 1/f noise parameter Kf does not show dramatic variations across different CMOS generations and foundries in NMOS. kf 1/f noise parameter αf 1/f noise slope-related coefficient ( 0.85 in NMOS,  1 – 1.1 in PMOS) saluti

White noise in 65 nm CMOS Evaluated in terms of the equivalent channel thermal noise resistance: αw excess noise coefficient n proportional to ID(VGS) subthreshold characteristic γ channel thermal noise coeff. aw close to unity for NMOS and PMOS with L > 65 nm  no sizeable short channel effects in the considered operating regions (except for 65 nm devices with aw ≈1.3 ) Negligible contributions from parasitic resistances

White noise in 65 nm CMOS

The analog front-end at extreme total ionizing dose
Among other effects, PMOSFETs (especially minimum size ones) show a large transconductance degradation, which becomes very steep over 100 Mrad (partial recover after annealing) This is probably not so critical for the design of analog blocks, where minimum size transistors can be avoided if necessary; the study of radiation effects on noise is ongoing Damage mechanisms have yet to be fully understood; they appear to be less severe at the foreseen operating temperature of the pixel detector at HL-LHC (about -15 °C) CPPM data with X-rays (Fermilab and Padova studying radiation effects with other sources) nmos : 120n/60n T = 25°C T = -15°C pmos : 120n/60n T = 25°C T = -15°C

Total ionizing dose effects in NMOSFETs: lateral leakage
ciao Total ionizing dose effects in NMOSFETs: lateral leakage In NMOSFETs edge effects due to radiation-induced positive charge in the STI oxide generate sidewall leakage paths. Shaneyfelt et al, “Challenges in Hardening Technologies using Shallow-Trench Isolation” IEEE TNS, Dec. 1998 L Lateral transistors have the same gate length as the main MOSFET NMOS finger Drain Multifinger NMOS n+ Gate Drain poly Gate Source n+ Source STI Lateral parasitic devices Main transistor finger saluti

Block diagram of the front-end chip
for signal processing in the BaBar vertex detector

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