1. Field Effect Transistors: Operation, Circuit Models, and Applications
CHAPTER 11
AC Power
Field Effect Transistors: Operation, Circuit Models, and Applications

2. Classification of field-effect transistors
Figure 11.1
Figure 11.1
11-1

3. The n-channel enhancement MOSFET construction and circuit symbol
Figure 11.2
Figure 11.2
11-2

4. Channel formation in NMOS transistor: (a) With no external gate voltage, the source-substrate and substrate-drain junctions are both reverse biased, and no conduction occurs; (b) when a gate voltage is applied, charge-carrying electrons are drawn between the source and drain regions to form a conducting channel.
Figure 11.3
Figure 11.3
11-3

5. Regions of operation of NMOS transistor
Figure 11.4
Figure 11.4
11-4

6. 11-5 Drain characteristic curves for a typical NMOS transistor with
VT = 2 V and K = 1.5 mA/V2
Figure 11.5
Figure 11.5
11-5

7. The n-channel enhancement MOSFET circuit and drain characteristic for Example 11.1
Figure 11.6
Figure 11.6
11-6

8. The p-channel enhancement-mode field-effect transistor (PMOS)
Regions of operation for PMOS transistor
Figure 11.9
Figure 11.8
Figure 11.8
Figure 11.8, 11.9
11-7

9. Typical common-drain and common-source MOSFET amplifiers
MOSFET transconductance parameter
Figure 11.11
Figure 11.10
Figure 11.10, 11.11
11-8

10. MOSFET small-signal model
Figure 11.13
Figure 11.13
11-9

11. CMOS inverter approximate by ideal switches: (a) When vin is “high,”
vout is tied to ground; (b) when
vin is “low,” vout is tied to VDD
Figure 11.14
Figure 11.15
Figure 11.14, 11.15
11-10

12. Figure 11.18
Figure 11.18
11-11

13. Figure 11.19
Figure 11.20
Figure 11.19, 11.20

14. Symbol for bilateral FET analog gate
MOSFET analog switch
Symbol for bilateral FET
analog gate
Figure 11.22
Figure 11.23
Figure 11.22, 11.23
11-12