1. FED FE-FPGA Code Development Progress Report
Fake Event code completed – June Requires additional test s/w for testing the phase shift and various fake event data.
Zero Suppression Light code (Phase I ) completed in July Replacement of the 2-byte packet length by a 1-byte number of clusters on hold.
ZS Lite initial tests successful. Requires additional test s/w.
Data Width Reduction options implemented. Requires tests.
Extensive VME Block Transfer tests have been carried to identify the bottlenecks and pitfalls.
SBS card repairs have been abandoned due to the refusal of SBS to supply technical information.
O. Zorba
CMS 29/09/2005
© Imperial College London

2. Future Work Complete the Fake Event code tests.
Complete the ZS Lite and Data Width Reduction code tests.
Start the hardware integration of the FEDs, Trigger, FMM, S-Link, etc. modules.
Develop the code to communicate with the Delay FPGA to initiate the Spy Channel data capture.
O. Zorba
CMS 29/09/2005
© Imperial College London