1. Xilinx XC9500 CPLDs Technology XC9500 CPLDs DESIGN PROTOTYPING TEST
MANUFACTURE
This foil provides an introduction and spells out the “Total Product Life Cycle” concept. The point is that XC9500 parts deliver capabilities for today’s designer who must anticipate needs for a wide spectrum of manufacturing and customer needs: Prototyping, Test, Manufacture and Field Upgrade as well as Design!
For design, a flexible, fast CPLD able to handle lots of today’s problems.
For prototyping, the ability to make changes in a design after the PCB has been produced.
For Testing, an advanced systematic capability with full support.
For manufacturing, the ability to handle multiple different production flows with the ability to adapt to changing methods.
For field upgrade, a way to inexpensively make upgrades and adjustments when the production units are already installed!
FIELD UPGRADE
Technology

2. Designer’s Needs- Today
In-System Programming
Testability
Design changes without PCB changes
Mixed 5V/3.3V I/Os
Robust Resource Assignment
Multiple speeds/densities in identical pinouts
Wide spectrum of packages
This is a partial list and varies among the many designers using CPLDs today. The most frequently requested feature is ISP, to eliminate sockets and programmer dependence. Additional testability is very desirable, assuring the best quality is delivered to customers. Prototyping without having to rework PCBs is clearly an advantage. The ability to combine both 5V and 3.3V I/Os through a simple interfacing chip is also very important. High endurance reprogramming may not actually be critical, because most people can get their prototypes working in less than 100 retries, but by having thousands of retries new applications and markets will be available. Finally, supplying several speed grades and densities in identically pinned packages permits designers to have multiple dimensions to which they can drive their designs.

3. Designer’s Needs- Tomorrow
Electrical signal management
Enhanced testability
High volume ASIC path
High endurance reprogramming
Internal revision management
Remote upgrade capability
Automatic, powerful software
This is a partial list and varies among the many designers using CPLDs today. The most frequently requested feature is ISP, to eliminate sockets and programmer dependence. Additional testability is very desirable, assuring the best quality is delivered to customers. Prototyping without having to rework PCBs is clearly an advantage. The ability to combine both 5V and 3.3V I/Os through a simple interfacing chip is also very important. High endurance reprogramming may not actually be critical, because most people can get their prototypes working in less than 100 retries, but by having thousands of retries new applications and markets will be available. Finally, supplying several speed grades and densities in identically pinned packages permits designers to have multiple dimensions to which they can drive their designs.

4. The First 5V Flash CPLD 5 V In-System Programming (ISP)
High performance
5ns pin-to-pin speed
125 MHz count frequency
Large density range
36 to 288 macrocells
Flexible architecture
optimized for pinlocking
global and product term clk,rst,oe
Most complete IEEE (JTAG)
Highest reprogramming and endurance
10,000 program/erase cycles
20 year retention
Clearly, the XC9500 is the first family providing 5V Flash based CPLD capability. Others have delivered 5V E EPROM and some have supplied 12V Flash, but Xilinx is the first to deliver 5V Flash.
Current speeds are to 5 nsec with 125 MHz, and the first phase family spans from 36 to 288 macrocells, but more important is that this family was architected specifically to address the special needs of In System Programming. Specifically, both the architecture and design S/W were developed to optimize pin locked design styles. As well, the JTAG interface delivered by XC9500 parts is substantially more complete than any other CPLD manufacturer’s. And finally, the Fast FLASH technology delivers over 10,000 program/erase cycles.

5. Why Flash Technology? Builds on EPROM experience
programming mechanism is the same
circuits and architecture are similar
Offers significant benefits due to
smaller cell size
increased programming/erase endurance
higher speed capability
Significant expansion in industry capacity in the late 90’s
PAL designers expect to pinlock, and many designers are frustrated when they cannot retain their pinouts. The list shown are the most commonly expected edits to be able to make, but many CPLD architectures can’t do these edits unless they are extremely under utilized. Typically, these are at 50% and below. Designers that frequently expect 90% or more utilization encounter pinlocking problems frequently. The real solution combines both architecture features as well as a S/W pinlocking strategy.

6. Smaller Cell Size with FastFlash
PAL designers expect to pinlock, and many designers are frustrated when they cannot retain their pinouts. The list shown are the most commonly expected edits to be able to make, but many CPLD architectures can’t do these edits unless they are extremely under utilized. Typically, these are at 50% and below. Designers that frequently expect 90% or more utilization encounter pinlocking problems frequently. The real solution combines both architecture features as well as a S/W pinlocking strategy.

7. In-System Programming
Ability to program the CPLD attached to PCB
Requires minimal additional pins
4 pins, shared with JTAG test capability
Requires 5 volt only
programmer self-contained on chip
Eliminated need for sockets
Eliminates pin mangling from reprogramming
Speeds up prototype development
PAL designers expect to pinlock, and many designers are frustrated when they cannot retain their pinouts. The list shown are the most commonly expected edits to be able to make, but many CPLD architectures can’t do these edits unless they are extremely under utilized. Typically, these are at 50% and below. Designers that frequently expect 90% or more utilization encounter pinlocking problems frequently. The real solution combines both architecture features as well as a S/W pinlocking strategy.

8. What is Pin-Locking?
Ability to retain device pin assignments for small to medium design changes
introducing a new variable to existing terms
adding input signals
inverting signals
introducing 1or 2 buried flip flops
adding p-terms
Requires a symmetric, uniform architecture
Requires software focus on pin-locking
PAL designers expect to pinlock, and many designers are frustrated when they cannot retain their pinouts. The list shown are the most commonly expected edits to be able to make, but many CPLD architectures can’t do these edits unless they are extremely under utilized. Typically, these are at 50% and below. Designers that frequently expect 90% or more utilization encounter pinlocking problems frequently. The real solution combines both architecture features as well as a S/W pinlocking strategy.

9. Pin-Locking is Key for ISP
Must retain pinouts as the design evolves
best done when the design software initially assigns pins
different from pinout pre-assigning
strong function of utilization in typical CPLD architectures
result of both architecture and software strategy
Pin-locking is valuable
eliminates or reduces PC Board rework
minimizes time to market, saves money
lowers designer frustration
Pinlocking is Key for ISP. This is because designers are literally doing their development right on the PCB. Pinouts must be kept, or the advantage is lost. With other architectures, there is a much stronger relationship to the utilization of the device and its ability to retain pinouts. Clearly, S/W is a key factor. Clearly, the architecture must be designed for this.
Pinlocking is valuable.

10. XC9500 Optimizes Pin-Locking
FastCONNECT
Switch Matrix
Function Block
Logic
Add another FB input Q
D/T
Fixed
Output
Pin
Add more logic
Add another pin
or FB output 36
Inputs
Inputs
To expand on the fundamental ideas, this picture shows how inputs are delivered to the FastCONNECT Switch Matrix. FastCONNECT subsequently selects a subset of up to 36 input signals to pass on to the Function Block. Within the Function Block, there are ample opportunities to collect p-terms as needed by the design.

11. XC9500 Supports Design Changes with Pin-Locking
XC9500 Feature
FastCONNECT switch matrix with 100% connectivity
XC9500 allows expansion up to 90 P-terms
36 total inputs are available plus FastCONNECT wired-and capability
100% connectivity
Design Change
Add another input pin or FB output
Add more logic in macrocell
Add additional input connections to the FB
Any buried logic can be moved
Pinlocking is Key for ISP. This is because designers are literally doing their development right on the PCB. Pinouts must be kept, or the advantage is lost. With other architectures, there is a much stronger relationship to the utilization of the device and its ability to retain pinouts. Clearly, S/W is a key factor. Clearly, the architecture must be designed for this.
Pinlocking is valuable.

12. XC9500 Applications JTAG systems rapid prototyping JTAG download
remote upgrade
Data communications
Computer systems
microprocessor interfacing
DRAM control
Embedded instrumentation
And, now we shift to some interesting applications!

13. XC9500 Rapid Prototyping Mount XC9500 device to PCB, fixing pinouts
Program via download cable (no programmer required)
Recompile design changes, erase and
reprogram multiple times
Debug logic with extended JTAG test
XC9500 advantages
Pin-locking architecture maintains pinouts
Endurance of 10,000 cycles
Extended JTAG test
XC9500
As you might expect, rapid prototyping is key. Developing designs fast so System software designers can evaluate their code is always important, so early PCB is critical to make today’s ridiculous design schedules! XC9500 permits development of the design while attached to the PCB. Then download the design through the cable, recompile changes and reload as needed. The single JTAG interface delivers efficient debug as well as testing. Finally, when the design is complete, the XC9500F parts are available for lower cost high volume production

14. Simplified Board Level Debug
Program
XC9500
Functional Test
Prototype
JTAG ISP solution supports FUNCTIONAL TEST of programmed devices
Made possible by JTAG INTEST instruction

15. Remote Upgrade Files arrive from remote source
File downloads
for embedded
update by
telecom link
MODEM
TDI
ROM/
FLASH
XC9500 uP
TCK
TMS
TDO
RAM
This is a classic. Companies need to download new CPLD configurations when the parts are already installed at a remote customer site. In this case, we show a modem driving the download data which subsequently lands in either on board EPROM or SRAM under control of an embedded microprocessor. the micro-P then handles downloading the CPLD. Note that this method could also be used for Xilinx FPGAs as well as XC9500 CPLDs. And, this is clearly not restricted to a telecom download. Fiber, radio or a simple serial line across a manufacturing floor or datacom link will also work.
Files arrive from remote source
Microprocessor manages JTAG protocol
Implements standard software

16. DRAM Control XC9500 High current drive to DRAMs
MICROPROCESSOR
Address
Address
DRAM
State
Machine CS M E O R Y
Refresh
Logic OE
RD/WR
RAS
Logic
RAS
Strobes
CAS
Logic
CAS
XC9500
Counter
High current drive to DRAMs
Multiple state machines (custom protocols)
Fast response

17. Reconfigurable Logic Build instrument into design
Logic can be deleted if needed
Instrument altered as needed (logic analyzer, BIST, etc.)
XC9500
This is an example of something some of our customers are doing - building a test instrument right into the end system. This eliminates having to go out and attach messy probes and get your shirt all dirty! The approach is to simply reserve some logic to use as an instrument. This can be as simple as a few observation “test probes” or as elaborate as a logic analyzer. In this diagram, there is a small signature analyzer built out of a shift register and some EX-OR gates. Other ideas include building up a data communication protocol analyzer or a performance monitor. Naturally, there is an applications note available on embedded instruments outlining this approach.

18. Foundation Series Software

19. XC9500 Expands the Manufacturing Process Capability
Industry’s most capable IEEE JTAG
USERCODE: built-in version control capability
IDCODE: identification of manufacturer, part number
INTEST: drive/read internal logic
HIGHZ: all outputs in high impedance mode

20. XC9500 Expands the Manufacturing Process Capability
Integrates device programming step into final board-level testing
completely eliminates stand-alone programming and mark steps
programmable using ATE, ISP cable, or µP
eliminates bent PQFP leads
concurrent programming of multiple devices
ISP board customization gives maximum flexibility

21. FastFLASH XC9500 Summary First 5V ISP CPLD using Flash technology
Architected for ISP
Flexibility
Industry’s Best Pin-Locking
Full-featured IEEE JTAG
Complete, easy-to-use software support
In closing, I think you will agree that the XC9500 delivers exactly those capabilities needed by today’s designers to provide the best solutions possible.
XC9500
From
The Best Total ISP Solution