1. EEE2135 Digital Logic Design Chapter 4. Combinational Logic Design
서강대학교
전자공학과

2. 1. Circuit Optimization
Goal: To obtain the simplest implementation for a given function
Optimization is a more formal approach to simplification that is performed using a specific procedure or algorithm
Optimization requires a cost criterion to measure the simplicity of a circuit
Distinct cost criteria we will use:
#Product terms in 2-level logic implementation
Literal count (for both 2-level and multi-level logics)
#Gates /#Gate inputs

3. Cost Function - #Product terms
In SOP representation
Primary goal to reduce #product terms by merging adjacent terms
2nd Literal Cost = 11
3rd Literal Cost = 10
The first solution is best

4. Cost Function - Literal Count
Literal – a variable or it complement
Literal count – #literal appearances in a Boolean expression corresponding to the logic circuit diagram
Examples:
F = BD + A B’ C + A C’D’ L = 8
F = BD + A B’ C + A B’D’ + ABC’ L = 11
F = (A + B)(A + D)(B + C + D’)( B’ + C’ + D) L = 10
Which solution is best?
2nd Literal Cost = 11
3rd Literal Cost = 10
The first solution is best

5. Cost Function - Gates/#Gate Inputs
#Gate inputs -# inputs to the gates in the implementation corresponding exactly to the given equations.
(G - inverters not counted, GN - inverters counted)
For SOP and POS equations, it can be found from the equation(s) by finding the sum of:
All literal appearances
#terms excluding terms consisting only of a single literal (G)
Optionally, #distinct complemented single literals (GN).
G = 15, GN = 18 (second value includes inverter inputs)
G = 14, GN = 17
1st solution is best

6. 2. K-Map Method Karnaugh Map
A modified truth table for minimal SOP, POS expression by visual inspection
Logical adjacency : cell grouping
- Row (column) labels forms a Gray code
Minimization procedure
Identify all PIs by encircling appropriate max-sized groups of 1-cells
Select a min set of PI groups that cover all the 1-cells
(when ties , select one that has lowest literals counts)
* A group of 1-cells denoted by a product term and not in a larger product group is a PI

7. Two-level SOP min. problem is solved by a minimal PI cover
EPI : a PI that covers 1-cell or min term that is not covered by any other PI
Ex)
Minimization with dc conditions
certain input combinations never occur
certain inputs occur only under circumstances s.t. output will not influence the system
Usually dc conditions are not given explicitly
ex) BCD-to-7-segment driver

8. a a b w f b c w d w g e e c w f g d (a) Code converterf b c w 1 d w g 2 e e c w 3 f g d
(a) Code converter
(b) 7-segment display w w w w a b c d e f g 3 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
(c) Truth table

9. Petrick’s Method (for PI selection) : not important
Method for finding a minimal cover
Expresses all the covering conditions that must be satisfied
ex)
Each term represents a cover of M by p
Select the term with the fewest PIs where literal count is minimal
Multiple-output Functions
Utilize shared terms - need mot be necessarily
Minimization – complicated

10. 3. Quine-McCluskey Procedure
Logic Simulation Minimization Programs
for functional correctness
simulation kernel + library + network description + input test pattern +modeling + simulation control
Minimization programs
for two-level
exact minimization (less than 20 variables) - McBOOLE
approximate minimization - ESPRESSO
for multi-level (approximate min.)
ESPRESSO-MV
MIS and SIS

11. 2) Algorithm Sketch Using code words {0,1,-}
Phase 1: PI identification
Each codeword with k 1’s is compared to all codewords with matching dashes and k+1 1’s
Phase 2: PI selection
cover table or PI table
Row dominance and column dominance
(delete dominated row) (delete dominating column)

12. 3) Quine-McCluskey Method
Uses the logical adjacency property
Compares each term with all the others, combine them if possible
Algorithm description
Phase1 (PI identification): Form a list of all minterms and dc terms Divide into groups ( contains minterms & dc terms with m 1’s)
Compare each entry in and Merge any two adjacent terms and add it to group of in
Any unchecked entries in are PIs.
Repeat steps II and III until is empty
Phase 2 (PI selection)
Set up a cover table T, =1, if covers j-th minterm
Identify essential rows of T and add to solution set S. Reduce T by removing essential rows, all columns covered by these rows
If T is empty, S is the solution. Otherwise, go to step VII.
Using the branch method, select a minimum-cost subset of the remaining rows to (PIs) add to S

13. Example: f(a, b, c, d) = m(0,2,4,5,6,9,10) + d(7,11,12,13,14,15)
1) Phase 1: PI Identification L0 L1
Group 
Group 
Group2
Group3
Group
Group0 (0,2)
Group1
Group2
Group3

14. Example: f(a, b, c, d) = m(0,2,4,5,6,9,10) + d(7,11,12,13,14,15)
Group 
Group 
4  0100
Group2
Group3
Group
Group0 (0,2)
(0,4)
Group1
Group2
Group3

15. Example: f(a, b, c, d) = m(0,2,4,5,6,9,10) + d(7,11,12,13,14,15)
Group 
Group 
4  0100
Group2
6  0110
Group3
Group
Group0 (0,2)
(0,4)
Group1 (2,6)
Group2
Group3

16. Example: f(a, b, c, d) = m(0,2,4,5,6,9,10) + d(7,11,12,13,14,15)
Group 
Group 
4  0100
Group2
6  0110
10  1010
Group3
Group
Group0 (0,2)
(0,4)
Group1 (2,6)
(2,10)
Group2
Group3

17. Example: f(a, b, c, d) = m(0,2,4,5,6,9,10) + d(7,11,12,13,14,15)
Group 
Group 
4  0100
Group2
5  0101
6  0110
9  1001
10  1010
12  1100
Group3
7 
11  1011
13  1101
14 1110
Group4 15 1111
Gruop0 (0,2)
(0,4)
Group1 (2,6)
(2,10)
(4,5)
(4,6)
(4,12)
Group2 (5,7)
(5,13)
(6,7)
(6,14)
(9,11)
(9,13)
(10,11)
(10,14)
(12,13)
(12,14)
Group3 (7,15)
(11,15)
(13,15)
(14,15) 111-

18. Example: f(a, b, c, d) = m(0,2,4,5,6,9,10) + d(7,11,12,13,14,15)
Group 
Group 
4  0100
Group2
5  0101
6  0110
9  1001
10  1010
12  1100
Group3
7 
11  1011
13  1101
14 1110
Group4 15 1111
Gruop0 (0,2) 
(0,4) 
Group1 (2,6) 
(2,10)  -010
(4,5) 
(4,6) 
(4,12)  -100
Group2 (5,7) 
(5,13)  -101
(6,7) 
(6,14) 
(9,11) 
(9,13) 
(10,11)  101-
(10,14)  1-10
(12,13)  110-
(12,14)  11-0
Group3 (7,15)  -111
(11,15)  1-11
(13,15)  11-1
(14,15)  111-
Group (0,2,4,6)
0--0
Group (2,6,10,14)
(4,5,6,7) 
(4,5,12,13) 
(4,6,12,14) 
--10
01—
-10-
-1-0
Group2 (5,7,13,15) 
(6,7,14,15) 
(9,11,13,15)
(10,11,14,15)
(12,13,14,15) 
-1-1
-11-
1--1
1-1-
11--
Group3 L3
Group1 (4,5,6,7,12,13,14,15)

19. Example: f(a, b, c, d) = m(0,2,4,5,6,9,10) + d(7,11,12,13,14,15)
Group 
Group 
4  0100
Group2
5  0101
6  0110
9  1001
10  1010
12  1100
Group3
7 
11  1011
13  1101
14 1110
Group4 15 1111
(0,2) 
(0,4) 
(2,6) 
(2,10)  -010
(4,5) 
(4,6) 
(4,12)  -100
(5,7) 
(5,13)  -101
(6,7) 
(6,14) 
(9,11) 
(9,13) 
(10,11)  101-
(10,14)  1-10
(12,13)  110-
(12,14)  11-0
(7,15)  -111
(11,15)  1-11
(13,15)  11-1
(14,15)  111-
(0,2,4,6)
0--0
(2,6,10,14)
 (4,5,6,7)
 (4,5,12,13)
 (4,6,12,14)
--10
01—
-10-
-1-0
 (5,7,13,15)
 (6,7,14,15)
(9,11,13,15)
(10,11,14,15)
 (12,13,14,15)
-1-1
-11-
1--1
1-1-
11--
PI0 (0,2,4,6)
PI1 (2,6,10,14)
PI2 (4,5,6,7,12,13,14,15)
-1--
PI3 (9,11,13,15)
PI4 (10,11,14,15)
(4,5,6,7,12,13,14,15) -1--

20. 2) Phase 2: PI Selection a. Cover Table
b. EPI = PI0 + PI2 + PI3 = a’d’ + b + ad
c. To cover m10, PI1 (=cd’ ) or PI4 (=ac) should be selected
m0 m2 m4 m5 m6 m9 m10
PI0(0--0)
PI1(--10)
PI2(-1--)
PI3(1--1)
PI4(1-1-) x x x x x x x x x x x x

21. 4. Design Procedure Specification
Write a specification for the circuit if not already available
Executable specification more desirable
Formulation
- Derive an initial Boolean equations (or TT) that define the required functions between inputs/outputs
Technology Independent Optimization
Apply 2-level and multiple-level optimization
Draw a logic diagram or provide a netlist for the resulting circuit using generic logic gates
Technology Dependent Optimization and Technology Mapping
- Perform technology specific optimization and map the logic diagram or netlist to the implementation technology selected
Verification
- Verify the correctness of the design

22. Design Example Specification BCD to Excess-3 code converter
Transforms BCD code for the decimal digits to Excess-3 code for the decimal digits
BCD code words for digits 0 through 9: 4-bit patterns 0000 to 1001, respectively
Excess-3 code words for digits 0 through 9: 4-bit patterns consisting of 3 (binary 0011) added to each BCD code word
Implementation:
multiple-level circuit
NAND gates (including inverters)

23. Formulation
Conversion of 4-bit codes can be most easily formulated by a truth table
Variables - BCD: A,B,C,D
Variables - Excess-3: W,X,Y,Z
Don’t Cares - BCD to 1111

24. w z y x Technology Independent Optimization C B A D
a. 2-level using K-maps
W = A + BC + BD
X = B’C + B’D + BC’D’
Y = CD + C’D’
Z = D’
G = = 23
b. Perform extraction, finding factor
T1 = C + D
W = A + BT1
X = B’T1 + BC’D’
G = = 19
c. Additional Transformation
T1 ‘ = C’D’ G becomes 16 B C D A 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 X w z y x

25. Technology Mapping
- Mapping with a library containing inverters and 2-input NAND, 2-input NOR, and 2-2 AOI gates A B C D W X Y Z

26. 5. Technology Mapping Chip design styles Cells and cell libraries
Mapping techniques
NAND gates
NOR gates
Multiple gate types
Programmable logic devices
Verification

27. 1) Chip Design Styles FGPA
Full custom - the entire design of the chip down to the smallest detail of the layout is performed
Expensive
Justifiable only for dense, fast chips with high sales volume
Standard cell - blocks have been designed ahead of time or as part of previous designs
Intermediate cost
Less density and speed compared to full custom
Gate array/Sea-of-Gates: regular patterns of gate transistors that can be used in many designs built into chip - only the interconnections between gates are specific to a design
Lower cost
Less density compared to full custom and standard cell
FGPA

28. 2) Cell Libraries Cell : a pre-designed primitive block
Cell library : a collection of cells available for design using a particular implementation technology
Cell characterization
A detailed specification of a cell for use by a designer
Often based on actual cell design and fabrication and measured values
Cells are used for gate array, standard cell, and in some cases, full custom chip design

29. e. Typical Cell Characterization Components
Schematic or logic diagram
Area of cell - Often normalized to the area of a common, small cell such as an inverter
Input loading (in standard loads) presented to outputs driving each of the inputs
Delays from each input to each output
One or more cell templates for technology mapping
One or more hardware description language models
If automatic layout is to be used:
Physical layout of the cell circuit
A floorplan layout providing the location of inputs, outputs, power and ground connections on the cell

30. Example Cell Library Cell Name Schematic Normalized Area Typical Input
Load
Input-to-
Output
Delay
Basic
Function
Templates
Inverter
1.00
0.04 1
0.012 3 SL
2NAND
1.25
0.05
0.014
2NOR
0.06
0.018
2-2 AOI
2.25
0.95
0.07
0.019

31. 3) Mapping: to NAND gates
Assumptions:
Gate loading and delay are ignored
Cell library contains an inverter and n-input NAND gates, n = 2, 3, …
An AND, OR, inverter schematic for the circuit is available
The mapping is accomplished by:
Replacing AND and OR symbols,
Pushing inverters through circuit fanout points, and
Canceling inverter pairs

32. NAND Mapping Algorithm
Replace ANDs and ORs:
Repeat the following pair of actions until there is at most one inverter between :
A circuit input or driving NAND gate output, and
The attached NAND gate inputs.

34. 6. Delay 1) Delay Models At a net node: Rising/falling delay
Port-to-port:
Transport delay - a change in the output in response to a change on the inputs occurs after a fixed specified delay
Inertial delay - similar to transport delay, except that if the input changes such that the output is to change twice in a time interval less than the rejection time, the output changes do not occur. Due to
Capacitance charge /discharge
Unbalance between rising/falling delay
Models typical electronic circuit behavior, namely, rejects narrow “pulses” on the outputs
c. Path Delay

35. 2) Delay Model Example A B A B: No Delay (ND) a b c d e Transport
Delay (TD)
Inertial
Delay (ID) 2 4 6 8 10 12 14 16
Time (ns)
Propagation Delay = 2.0 ns Rejection Time = 1 .0 ns

36. Waveforms for logic gates
Transport delay V DD
Gnd in
out
50%
90%
10% t r f
Transport delay
Vin
Vout if delay = 0
Vout

37. DC Transfer characteristic of a CMOS inverterx OL = OH DD T IL IH – ( ) 2 —
Slope 1
y = x
VDD 2

38. 3) Fanouts * Fanout can be defined in terms of a standard load
1 standard load equals the load contributed by the input of one inverter.
Transition time -time required for the gate output to change from H to L tHL, or from L to H, tLH (falling /rising delay)
The maximum fanout that can be driven by a gate is the number of standard loads the gate can drive without exceeding its specified maximum transition time
The fanout loading affects the gate’s propagation delay
Example:
One realistic equation for tpd for a NAND gate with 4 inputs is: tpd = SL ns
SL is the number of standard loads the gate is driving, i. e., its fanout in standard loads. SL = 4, tpd = ns

39. 7. Delay Analysis : delay of gate j; Single Component Delay
Rising / falling time
Transport delay and Intrinsic ( inertial ) delay
Multiple Component Delay : Path Delay
Delay for a signal to propagate from a net node to another net thru gates following a specified path
Critical paths/Critical section
paths with the max delay in a circuit
Paths whose delays exceed the given specification (max. allowed delay)
Analysis
Signal Ready (Arrival) Time
: delay of gate j;
K : set of fanins to gate j

40. Delay Analysis II. Slack
- amount of delay that can be added to a node without violating the given specification (maximum allowed delay)
for output nodes
s(vi) = max. allowed delay – r(vi)
for internal nodes
vj1
vk2
vk1
vk3
vj2 vi
vk: gates that drive the gates (vj) driven by vi

41. Example: Maximum allowed delay = 11ns
- Numbers inside circles represent the delay (in ns) associated with the gates 3 4 5 2
t=0 v a b c d e f g h

42. { { { { Solution I. Signal arrival time II. Slack
s(vf) = 11 – 12 = -1, s(vg) = 11 – 10 = 1, s(vh) = 11 – 12 = -1
s(vd) = min s(vf) + max(r(vd), r(ve)) - r(vd) = = 1
s(vg) + max(r(vd)) - r(vd) = 1
s(ve) = min s(vf) + max(r(vd), r(ve)) - r(ve) = = -1
s(vh) + max(r(vc), r(ve)) - r(ve) = -1
s(va) = s(vd) + max(3, 4) - 3 = 2
s(vb) = min s(vd) + max(3, 4) = 0 s(vc) = min s(ve) + max(4, 5) -5 = -1
s(ve) + max(4, 5) s(vh) + max(9, 5) -5 { { { {

43. Analysis Results : Critical Section in Red4 3 v a b c d e f g h 3 4 5 2 v v a f 3 3 v 3 d 2 2 v v g 4 4 4 b 4 v e v v 3 h c 5 5
t=0

44. Discussions a. Why do we need path analysis ?
Consider the RT model of a digital system
The maximum delay of all the combinational circuits in the datapath determines the maximum clock frequency
- fc, max < 1/ max(dcc) (* This will be refined later)
b. We must eliminate the critical sections by
Resizing the transistors to reduce the delay of the gates
Restructuring/Redesigning
clock
CC2
CC1
register