1. Mapping area of the 36 PMT
9 PMT
9 PMT
9 PMT
9 PMT

2. PMT >DAQ WA105 link 9 PM Front-end PMT board ParisRoc
T: Trigger flag = 1 bit, arrival at T0 in FPGA.
TD: Timing Data = 51bits x 9 (11,5µs)
Clk: clock at 40Mhz with enable (5.5µs duration)
- Start at TO,
- End at T0 + 5µs + 18x25ns(pipeline ADC)
CD: Charge Data = 40Mhz
- 9 CD in // (9 ADC outputs)
- 5µs = Mhz
To: Trigger output = T
FED: Front-End Data to DAQ
= 51 bitsx9 + 12bitsx9x200
= Mhz copper
= µs BAD (too long)
RC-PA
AD9249 T TD CD
Clk
FPGA To
FED
DAQ

3. PMT >DAQ WA105 link Proposal 1
Front-end
PMT
board
ParisRoc
T: Trigger flag = 1 bit, arrival at T0 in FPGA.
TD: Timing Data = 51bits x 9 (11,5µs)
Clk: clock at 40Mhz with enable (5.5µs duration)
- Start at TO,
- End at T0 + 5µs + 18x25ns(pipeline ADC)
CD: Charge Data = 40Mhz
- 9 CD in // (9 ADC outputs)
- 5µs = Mhz
To: Trigger output = T
FED: Front-End Data to DAQ
= 51 bitsx9 + 12bitsx9x200
= Ghz optic fiber
= 22 µs OK
RC-PA
AD9249 T
TD(40Mhz) CD
Clk(40Mz)
5,5µs
11,5µs
FPGA To
FED
22µs
DAQ

4. PMT >DAQ WA105 link Proposal 2
T: Trigger flag = 1 bit, arrival at T0 in FPGA.
TD: Timing Data= 51bits x 9 (11,5µs)
Clk: clock at 40Mhz with enable (5.5µs duration)
- start at TO,
- end at T0 + 5µs + 18x25ns(pipeline ADC)
CD: Charge DATA = 40Mhz
- 9 CD in // (9 ADC outputs)
- 5µs = Mhz
To: Trigger output = T
CFED: Charge Front-end Data to DAQ
= 12bitsx9x200
= Mhz copper
= 216 µs OK
TFED: Trigger Front-end Data to DAQ
= 51 bitsx9
= Mhz copper
= 4,6 µs OK
9 PM
Front-end
PMT
board
ParisRoc
RC-PA
AD9249 T
TD(40Mhz) CD
Clk(40Mz)
5,5µs
11,5µs
FPGA To
CFED
TFED
216µs
4,6µs
DAQ

5. Step 1 2015-2017 2 PMT FE Board 2 PMT FE Board PMT HV 1 chimney
PMT signal
4 chimneys
9 cables/ch
PMT HV
1 chimney
36 HV cables

6. Step
4 PMT
FE Board

7. Block task I/F DAQ PMT Power µTCA LInk Tray cable (chimney) PMT
Front-end
Board
PMT

8. PMT Power Resp: Thomas Patzak (APC) HV or LV I/F DAQ PMT Power
Remote control on Power supply
or in FE board
Nbr of channel
I/F DAQ
µTCA
PMT Power
LInk
Tray
cable
(chimney)
PMT
Front-end
Board
PMT

9. I/F DAQ Block Resp: Cyril Drancourt (LAPP) Use part of LEM DAQ Board
FPGA ressource
Hardware to PMT FE Board
I/F DAQ
µTCA
PMT Power
LInk
Tray
cable
(chimney)
PMT
Front-end
Board
PMT

10. DAQ WA105 schematic
PMT
DAQ
µTCA Crate

11. DAQ PMT WA105 1 Carte µTCA PMT Electronic (can be a part Detector PMT
Of FPGA
EP5CE)
Connectors
1 Carte µTCA
Detector
PMT
(36 PM)
Crate
µTCA
Common logic
With DAQ
LEM board
Link to PMT FE Board

12. Block Link DAQ <>FE PMT
Resp: Cyril Drancourt(LAPP)
& Pablo Marin Jimenez (APC)
Optic or copper
Nbr of link (data, synchro, clock)
Bandwith calculation
Altera protocol link
I/F DAQ
µTCA
PMT Power
LInk
Tray
cable
(chimney)
PMT
Front-end
Board
PMT

13. Synchronisation Cartes DAQ LEM Cartes DAQ PMT Synchro à 400ns
entre les cartes PMT
Synchro à 400ns
entre les
cartes LEM

14. PMT Front-End Board Resp: Yingtao (OMEGA/IPNO)
& Pablo Marin Jimenez (APC)
Composant choise (ParisRoc, ADC, FPGA)
Remote power PMT or not
Board location
Altera protocol link
I/F DAQ
µTCA
PMT Power
LInk
Tray
cable
(chimney)
PMT
Front-end
Board
PMT

15. PMT detector Resp: ???(Ciemat) & Pierre Prat(APC) I/F DAQ PMT Power
PM choise
Signal
Cabling in LAR
I/F DAQ
µTCA
PMT Power
LInk
Tray
cable
(chimney)
PMT
Front-end
Board
PMT

16. Chimney Resp: ???(Zurich) & ?(APC) ?(LAPP) I/F DAQ PMT Power
Tray in step1
Tray in step2
HV solution
I/F DAQ
µTCA
PMT Power
LInk
Tray
cable
(chimney)
PMT
Front-end
Board
PMT