1. ESD Stress Models

2. ESD Stress Models … Concepts Overall
Human Body Model (HBM)
A charged person discharges to a chip or discharges to the ground through a chip.
Machine Model (MM)
A charged machine discharges to a chip or discharges to the ground through a chip.
Charged Device Model (CDM)
A chip (or internal circuit of the chip ) becomes charged and discharges to the ground.
IEC
ESD stress is discharged to a chip when it is on the system ( or on the board ).

3. Chip Level ESD Stress Models … HBM, MM, CDM+ + -

4. Human Body Model (HBM) … Definition & Modeling
A charged Person discharges to a device or discharges to the ground through a device.
High Voltage
Supply
Charging
Resistor
50 ~ 100MΩ
Discharging
1500Ω
DUT
Charge
Storage
Capacitor
100pF
The HBM ESD Stress is developed with a 100pF capacitor discharging through a 1500 resistor to the device.
The use of 1500 resistor implies that the human body model approximates a current source.
The HBM ESD stress model is prescribed in JEDEC's JESD22-A114, the  MIL-STD-883 Method 3015 and  ESD Association's ESD STM5.1.

5. Human Body Parameter : Why 100pF Capacitor & 1500 Resistor ?
Human Body Model (HBM) … Why 1500Ω and 100pF ?
Human Body Parameter : Why 100pF Capacitor & 1500 Resistor ?
Human Body Parameters
Extracted from a Group of Workers
Standing Erect
The human body standing capacitance is found to range 100 ~ 250pF The human body resistance is found to range 100 ~ 2500.
The field failure thresholds can be significantly different from those determined with the standard HBM parameters.
( In a typical environment the person may be seated rather than standing, which has the effect of increasing capacitance and reducing the series resistance. )

6. The HBM Discharge Waveform is Characterized as
Human Body Model (HBM) … Discharge Waveform
Human Body Model Discharging Waveform
The HBM Discharge Waveform is Characterized as
Rise Time = 2 ~ 10nsec, Duration  150nsec, Peak Current  Charging Voltage /1500 .

7. Machine Model (MM) … Definition & Modeling
A charged Machine discharges to a device or discharges to the ground through a device
Charging
Resistor
Parasitic
Inductor
50 ~ 100MΩ
500nH
DUT
Charge
Storage
Capacitor
High Voltage
Supply
200pF
The MM ESD Stress is developed with a 200pF capacitor discharging through a 500nH inductor to the device.
The absence of resistor implies that the machine model approximates a voltage source.
The MM ESD stress model is prescribed in JEDEC's JESD22-A115 and  ESD Association's ESD STM5.2.

8. Machine Model (MM) … Discharge Waveform
Machine Model Discharging Waveform
The MM Discharge Waveform is Characterized as
Rise Time > 10nsec, Duration ~ 50nsec, Peak Current  200V .

9. Charged Device Model (CDM) … Definition & Modeling
A chip (or internal circuit of the chip ) becomes charged and discharges to the ground. +
The CDM ESD stress is not to be modeled easily, because the charges are generated within the device in various ways.
The CDM ESD stress can sometimes even be more destructive than HBM ESD (despite its shorter pulse duration) because of its high current.
The CDM ESD stress model is prescribed in JEDEC's JESD22-C101 and  ESD Association's ESD STM5.3.1.

10. Field Induced CDM Simulator
Charged Device Model (CDM) … Pre-Charging
Field Induced CDM Simulator
Current procedures for charging the device includes ‘ direct charging method ’ and ‘ field induced method ’.
(1) Direct charging method : Charge is applied to a device by direct contact with current supplier
(2) Field Induced method : Entire package is charged by induction in the presence of an electric field

11. Charged Device Model Discharging Waveform
Charged Device Model … Discharge Waveform
Charged Device Model Discharging Waveform
- The CDM discharging waveform is characterized by very rapid rise time, very high peak current, and the oscillating decay of the discharge.
- Compared to the HBM discharge at the same potential, there is much less energy in a CDM discharge.
( There is about 75:1 difference in the capacitance between HBM and CDM. )
However, the very rapid time tends to produce large potential differences between the traces of the device.

12. Comparison of HBM, MM. CDM
Model
HBM
Human Body Model MM
Machine Model
CDM
Charged Device Model
Origin
JESD22-A114
ESD STM5.1
MIL-STD-883 Method 3015
JESD22-A115
ESD STM5.2
JESD22-C101
 ESD STM5.3.1
RLC
1500Ω, 0H, 100pF
0Ω, 500nH, 200pF
~1Ω, ~1nH, 1 ~ 20pF
Peak Current
1.3 ~ 1.5A @ 2000V
4.0 ~ 8.0A @ 200V
15.0 ~ 20.0A @ 500V
Rise Time
 10nsec
> 10nsec
~ 100psec
Duration
 150nsec
 50nsec
1 ~ 2nsec
Bandwidth
 2MHz
 10MHz
 1GHz
Thermal Energy
Quite High
High
Low
Voltage Shock
Moderate

13. Time (nsec) Current (A)
Comparison of HBM, MM. CDM
Time (nsec)
Current (A) 50
CDM 1000V
MM 200V
HBM 2000V 10 20 30 40
-10 -5 5 15

14. System Level ESD Stress Models ( IEC6100-4-2 ) … Definition & Modeling
ESD stress is discharged to a chip when it is on the system ( or on the board ).
High Voltage
Supply
Charging
Resistor
50 ~ 100MΩ
Discharging
330Ω
Charge
Storage
Capacitor
150pF
DUT
The IEC type ESD Stress is developed with a 150pF capacitor discharging through a 330 resistor on the system ( or on the board ).
The IEC type ESD stress is applied on the system with ( or on the board ) with a VLSI chip exposed ( or un-exposed ) to the ESD stress.

15. IEC61000-4-2 ESD Stress Waveform
System Level ESD Stress Models ( IEC ) … Waveform and Classification
IEC ESD Stress Waveform
IEC ESD Pass Level Classification
The IEC type ESD Stress’ waveform appears to be the combination of HBM, MM and CDM type ESD stresses.

16. ESD Stress Zapping Spot on Display Module
System Level ESD Stress Models ( IEC ) … Correlation between Module ESD and Chip ESD
ESD Stress Zapping Spot on Display Module
Voltage Stress on Chip’s Pin upon IEC
Correlation factors between the system level ESD ( IEC ) and the chip level ESD are to be function of module’s RLC values.
That is, the correlation coefficients are quite dependent on the module’s geometry, components’ material, position of zapping spot, etc.
It seems that the correlation factor is strongly dependent on the position of zapping spot.
For typical small DDI chip module, when the zapping spot is on the edge of the display panel, IEC type ESD stress with 4000V appears to amount to MM-like150 ~ 200V ESD stress.