Design for Testability Theory and Practice

Design for Testability Theory and Practice
Professors Adit Singh and Vishwani Agrawal Electrical and Computer Engineering The slide guide is available in the following file: slidesV4.3.ppt: PowerPoint 2000 format. Viewable also with PowerPoint ’97.

Presenters Copyright 2001 Agrawal & Bushnell
Adit D. Singh is James B. Davis Professor of Electrical & Computer Engineering at Auburn University, where he directs the VLSI Design & Test Laboratory. Earlier he has held faculty positions at the University of Massachusetts in Amherst, and Virginia Tech in Blacksburg. His research interests are in VLSI design, test, reliability and fault tolerance; he has published over a 100 papers in these areas and holds international patents that have been licensed to industry. He has also served as Chair/Co-Chair or Program Chair of over a dozen IEEE international conferences and workshops. Over the years he has taught approximately 50 short courses in-house for companies including IBM, National Semiconductor, TI, AMD, Advantest, Digital, Bell Labs and Sandia Labs, also at IEEE technical meetings, and through university extension programs. Dr. Singh currently serves on the Executive Committee of the IEEE Computer Society’s Technical Activities Board, on the Editorial Board of IEEE Design and Test, and is Vice Chair of the IEEE Test Technology Technical Council. He is a Fellow of IEEE and a Golden Core Member of the IEEE Computer Society. Vishwani D. Agrawal is James J. Danaher Professor of Electrical &Computer Engineering at Auburn University, Auburn, Alabama, USA. He has over thirty years of industry and university experience, working at Bell Labs, Rutgers University, TRW, IIT in Delhi, EG&G, and ATI. His areas of research include VLSI testing, low-power design, and microwave antennas. He has published over 250 papers, holds thirteen U.S. patents and has co-authored 5 books including Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits with Michael Bushnell at Rutgers. He is the founder and Editor -in-Chief of the Journal of Electronic Testing: Theory and Applications, was a past Editor -in-Chief of the IEEE Design & Test of Computers magazine, and is the Founder Editor of the Frontiers in Electronic Testing Book Series. Dr. Agrawal is a co-founder of the International Conference on VLSI Design, and the International Workshops on VLSI Design and Test, held annually in India. He served on the Board of Governors of the IEEE Computer Society in 1989 and 1990,and, in 1994, chaired the Fellow Selection Committee of that Society. He has received seven Best Paper Awards, the Harry H. Goode Memorial Award of the IEEE Computer Society, and the Distinguished Alumnus Award of the University of Illinois at Urbana-Champaign. Dr. Agrawal is a Fellow of the IETE-India, a Fellow of the IEEE and a Fellow of the ACM. He has served on the advisory boards of the ECE Departments at University of Illinois, New Jersey Institute of Technology, and the City College of the City University of New York. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Design for Testability – Theory and Practice
Three-Day Intensive Course Hyderabad, July 27-29, 2006 Day 1 AM Introduction Singh Basics of testing Singh Fault models Singh PM Logic simulation Agrawal Fault simulation Agrawal Testability measures Agrawal Day 2 AM Combinational ATPG Agrawal Sequential ATPG Agrawal PM Delay test Singh IDDQ testing, reliability Singh Day 3 AM Memory test Agrawal Scan, boundary scan Agrawal PM BIST Singh Test compression Singh Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Books on Testing M. Abramovici, M. A. Breuer and A. D. Friedman, Digital Systems Testing and Testable Design, Piscataway, New Jersey: IEEE Press, 1994, revised printing. M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Boston: Springer, Appendix C, pp , lists more books on testing. Also see D. Gizopoulos, editor, Advances in Electronic Testing: Challenges and Methodologies, Springer, 2005, volume 27 in Frontiers in Electronic Testing Book Series. N. K. Jha and S. K. Gupta, Testing of Digital Systems, London, United Kingdom: Cambridge University Press, 2002. L.-T. Wang, C.-W. Wu and X. Wen, editors, VLSI Test Principles and Architectures: Design for Testability, Elsevier Science, 2006. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Topics Introduction The VLSI Test Process Test Basics Stuck-at faults
Test generation for combinational circuits Automatic Test Pattern Generation (ATPG) Fault Simulation and Grading Test Generation Systems Sequential ATPG Scan and boundary scan Design for testability Timing and Delay Tests IDDQ Current Testing Reliability Screens for burn-in minimization Memory Testing Built in self-test (BIST) Test compression Memory BIST IEEE 1149 Boundary Scan Conclusion Books on testing View it as a slide show first. It will highlight important aspects of your presentation, and give you an example of a presentation that lives up to ITC presentation standards and guidelines. Virus checker: When we created this presentation guide it contained no known viruses. This file was checked by McAfee VShield 4.x software before being distributed to authors. You should use a good, up to date virus checker on this file, and any other file you import from an outside source. Make sure your virus checker’s data files are up to date, too. Keep in mind: the version of this file you are reading may be different from the version we checked! Confidentiality: We respect your copyright, and do not distribute your presentation before the conference. However, we cannot promise strict confidentiality of your presentation before the conference, because others have read access to our FTP sites. Do not include confidential information in your presentation. Test Slide: A test slide is included as a “hidden slide” after the end of this presentation. If you want to do a trial projection, ensure that your projector projects the entire slide, and that aspect ratios are correct. We will use the same test slide at the conference for setup of our projection equipment. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Introduction Many integrated circuits contain fabrication defects upon manufacture Die yields may only be 20-50% for high end circuits ICs must be carefully tested to screen out faulty parts before integration in systems Latent faults that cause early life failure must also be screened out through “burn-in” stress tests View it as a slide show first. It will highlight important aspects of your presentation, and give you an example of a presentation that lives up to ITC presentation standards and guidelines. Virus checker: When we created this presentation guide it contained no known viruses. This file was checked by McAfee VShield 4.x software before being distributed to authors. You should use a good, up to date virus checker on this file, and any other file you import from an outside source. Make sure your virus checker’s data files are up to date, too. Keep in mind: the version of this file you are reading may be different from the version we checked! Confidentiality: We respect your copyright, and do not distribute your presentation before the conference. However, we cannot promise strict confidentiality of your presentation before the conference, because others have read access to our FTP sites. Do not include confidential information in your presentation. Test Slide: A test slide is included as a “hidden slide” after the end of this presentation. If you want to do a trial projection, ensure that your projector projects the entire slide, and that aspect ratios are correct. We will use the same test slide at the conference for setup of our projection equipment. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

IC Testing is a Difficult Problem
Need 23 = 8 input patterns to exhaustively test a 3-input NAND 2N tests needed for N-input circuit Many ICs have > 100 inputs Only a very few input combinations can be applied in practice 3-input NAND 2100 = 1.27 x 1030 Applying 1030 tests at 109 per second (1 GHZ) will require 1021 secs = 400 billion centuries! View it as a slide show first. It will highlight important aspects of your presentation, and give you an example of a presentation that lives up to ITC presentation standards and guidelines. Virus checker: When we created this presentation guide it contained no known viruses. This file was checked by McAfee VShield 4.x software before being distributed to authors. You should use a good, up to date virus checker on this file, and any other file you import from an outside source. Make sure your virus checker’s data files are up to date, too. Keep in mind: the version of this file you are reading may be different from the version we checked! Confidentiality: We respect your copyright, and do not distribute your presentation before the conference. However, we cannot promise strict confidentiality of your presentation before the conference, because others have read access to our FTP sites. Do not include confidential information in your presentation. Test Slide: A test slide is included as a “hidden slide” after the end of this presentation. If you want to do a trial projection, ensure that your projector projects the entire slide, and that aspect ratios are correct. We will use the same test slide at the conference for setup of our projection equipment. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

IC Testing in Practice For high end circuits
A few seconds of test time on very expensive production testers Many thousand test patterns applied Test patterns carefully chosen to detect likely faults High economic impact -test costs are approaching manufacturing costs Despite the costs, testing is imperfect! View it as a slide show first. It will highlight important aspects of your presentation, and give you an example of a presentation that lives up to ITC presentation standards and guidelines. Virus checker: When we created this presentation guide it contained no known viruses. This file was checked by McAfee VShield 4.x software before being distributed to authors. You should use a good, up to date virus checker on this file, and any other file you import from an outside source. Make sure your virus checker’s data files are up to date, too. Keep in mind: the version of this file you are reading may be different from the version we checked! Confidentiality: We respect your copyright, and do not distribute your presentation before the conference. However, we cannot promise strict confidentiality of your presentation before the conference, because others have read access to our FTP sites. Do not include confidential information in your presentation. Test Slide: A test slide is included as a “hidden slide” after the end of this presentation. If you want to do a trial projection, ensure that your projector projects the entire slide, and that aspect ratios are correct. We will use the same test slide at the conference for setup of our projection equipment. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

How well must we test? Approximate order of magnitude estimates
Number of parts per typical system: 100 Acceptable system defect rate: 1% (1 per 100) Therefore, required part reliability 1 defect in 10,000 100 Defects Per Million (100 DPM) Requirement ~100 DPM for commercial ICs ~1000 DPM for ASICs View it as a slide show first. It will highlight important aspects of your presentation, and give you an example of a presentation that lives up to ITC presentation standards and guidelines. Virus checker: When we created this presentation guide it contained no known viruses. This file was checked by McAfee VShield 4.x software before being distributed to authors. You should use a good, up to date virus checker on this file, and any other file you import from an outside source. Make sure your virus checker’s data files are up to date, too. Keep in mind: the version of this file you are reading may be different from the version we checked! Confidentiality: We respect your copyright, and do not distribute your presentation before the conference. However, we cannot promise strict confidentiality of your presentation before the conference, because others have read access to our FTP sites. Do not include confidential information in your presentation. Test Slide: A test slide is included as a “hidden slide” after the end of this presentation. If you want to do a trial projection, ensure that your projector projects the entire slide, and that aspect ratios are correct. We will use the same test slide at the conference for setup of our projection equipment. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

How well must we test? Assume 2 million ICs manufactured with 50% yield 1 million GOOD >> shipped 1 million BAD >> test escapes cause defective parts to be shipped For 100 BAD parts in 1M shipped (DPM=100) Test must detect 999,900 out of the 1,000,000 BAD For 100 DPM: Needed Test Coverage = 99.99% View it as a slide show first. It will highlight important aspects of your presentation, and give you an example of a presentation that lives up to ITC presentation standards and guidelines. Virus checker: When we created this presentation guide it contained no known viruses. This file was checked by McAfee VShield 4.x software before being distributed to authors. You should use a good, up to date virus checker on this file, and any other file you import from an outside source. Make sure your virus checker’s data files are up to date, too. Keep in mind: the version of this file you are reading may be different from the version we checked! Confidentiality: We respect your copyright, and do not distribute your presentation before the conference. However, we cannot promise strict confidentiality of your presentation before the conference, because others have read access to our FTP sites. Do not include confidential information in your presentation. Test Slide: A test slide is included as a “hidden slide” after the end of this presentation. If you want to do a trial projection, ensure that your projector projects the entire slide, and that aspect ratios are correct. We will use the same test slide at the conference for setup of our projection equipment. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

DPM depends on Yield For Test Coverage: 99.99%
(Escapes 100 per million defective) - 1 Million 10% Yield 0.1 million GOOD >> shipped 0.9 million BAD >> 90 test escapes DPM = 90 /0.1 = 900 - 1 Million 90% Yield 0.9 million GOOD >> shipped 0.1 million BAD >> 10 test escapes DPM = 10/0.9 = 11 View it as a slide show first. It will highlight important aspects of your presentation, and give you an example of a presentation that lives up to ITC presentation standards and guidelines. Virus checker: When we created this presentation guide it contained no known viruses. This file was checked by McAfee VShield 4.x software before being distributed to authors. You should use a good, up to date virus checker on this file, and any other file you import from an outside source. Make sure your virus checker’s data files are up to date, too. Keep in mind: the version of this file you are reading may be different from the version we checked! Confidentiality: We respect your copyright, and do not distribute your presentation before the conference. However, we cannot promise strict confidentiality of your presentation before the conference, because others have read access to our FTP sites. Do not include confidential information in your presentation. Test Slide: A test slide is included as a “hidden slide” after the end of this presentation. If you want to do a trial projection, ensure that your projector projects the entire slide, and that aspect ratios are correct. We will use the same test slide at the conference for setup of our projection equipment. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

The VLSI Test Process Copyright 2001 Agrawal & Bushnell
Hyderabad, July 27-29, 2006 (Day 1)

Types of Testing Verification testing, characterization testing, or design debug Verifies correctness of design and of test procedure – usually requires correction to design Manufacturing testing Factory testing of all manufactured chips for parametric faults and for random defects Acceptance testing (incoming inspection) User (customer) tests purchased parts to ensure quality Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Verification Testing Ferociously expensive May comprise:
Scanning Electron Microscope tests Bright-Lite detection of defects Electron beam testing Artificial intelligence (expert system) methods Repeated functional tests Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Characterization Test
Worst-case test Choose test that passes/fails chips Select statistically significant sample of chips Repeat test for every combination of 2+ environmental variables Plot results in Shmoo plot Diagnose and correct design errors Continue throughout production life of chips to improve design and process to increase yield Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Manufacturing Test Determines whether manufactured chip meets specs
Must cover high % of modeled faults Must minimize test time (to control cost) No fault diagnosis Tests every device on chip Test at speed of application or speed guaranteed by supplier Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Burn-in or Stress Test Process:
Subject chips to high temperature & over-voltage supply, while running production tests Catches: Infant mortality cases – these are damaged chips that will fail in the first 2 days of operation – causes bad devices to actually fail before chips are shipped to customers Freak failures – devices having same failure mechanisms as reliable devices Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Types of Manufacturing Tests
Wafer sort or probe test – done before wafer is scribed and cut into chips Includes test site characterization – specific test devices are checked with specific patterns to measure: Gate threshold Polysilicon field threshold Poly sheet resistance, etc. Packaged device tests Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Sub-types of Tests Parametric – measures electrical properties of pin electronics – delay, voltages, currents, etc. – fast and cheap Functional – used to cover very high % of modeled faults – test every transistor and wire in digital circuits – long and expensive – main topic of tutorial Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Test Data Analysis Uses of ATE test data: Reject bad DUTS
Fabrication process information Design weakness information Devices that did not fail are good only if tests covered 100% of faults Failure mode analysis (FMA) Diagnose reasons for device failure, and find design and process weaknesses Allows improvement of logic & layout design rules Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Test Basics Input (a1, a2, a3 … an) is a test for fault a iff
f (x1, x2, …xn) fault free function fa (x1, x2, …xn) when fault is present x1 x2 x3 . xn DUT Input (a1, a2, a3 … an) is a test for fault a iff f (a1, a2, a3 … an) ≠ fa (a1, a2, a3 … an) Note: We are only interested in knowing if the DUT is faulty, not in diagnosing or locating the fault View it as a slide show first. It will highlight important aspects of your presentation, and give you an example of a presentation that lives up to ITC presentation standards and guidelines. Virus checker: When we created this presentation guide it contained no known viruses. This file was checked by McAfee VShield 4.x software before being distributed to authors. You should use a good, up to date virus checker on this file, and any other file you import from an outside source. Make sure your virus checker’s data files are up to date, too. Keep in mind: the version of this file you are reading may be different from the version we checked! Confidentiality: We respect your copyright, and do not distribute your presentation before the conference. However, we cannot promise strict confidentiality of your presentation before the conference, because others have read access to our FTP sites. Do not include confidential information in your presentation. Test Slide: A test slide is included as a “hidden slide” after the end of this presentation. If you want to do a trial projection, ensure that your projector projects the entire slide, and that aspect ratios are correct. We will use the same test slide at the conference for setup of our projection equipment. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Test Basics For an n input circuit, there are 2n input combinations.
Ideally we must test for all possible faulty functions. This will require an exhaustive test with 2n inputs x1 x2 x f Since we cannot apply the exhaustive test set our best bet is to target likely faults! View it as a slide show first. It will highlight important aspects of your presentation, and give you an example of a presentation that lives up to ITC presentation standards and guidelines. Virus checker: When we created this presentation guide it contained no known viruses. This file was checked by McAfee VShield 4.x software before being distributed to authors. You should use a good, up to date virus checker on this file, and any other file you import from an outside source. Make sure your virus checker’s data files are up to date, too. Keep in mind: the version of this file you are reading may be different from the version we checked! Confidentiality: We respect your copyright, and do not distribute your presentation before the conference. However, we cannot promise strict confidentiality of your presentation before the conference, because others have read access to our FTP sites. Do not include confidential information in your presentation. Test Slide: A test slide is included as a “hidden slide” after the end of this presentation. If you want to do a trial projection, ensure that your projector projects the entire slide, and that aspect ratios are correct. We will use the same test slide at the conference for setup of our projection equipment. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Test Basics Defects Faults and Errors
A Defect is a physical flaw in the device, i.e. a shorted transistor or an open interconnect A Fault is the logic level manifestation of the Defect, i.e. a line permanently stuck at a low logic level An Error occurs when a fault causes an incorrect logic value at a functional output View it as a slide show first. It will highlight important aspects of your presentation, and give you an example of a presentation that lives up to ITC presentation standards and guidelines. Virus checker: When we created this presentation guide it contained no known viruses. This file was checked by McAfee VShield 4.x software before being distributed to authors. You should use a good, up to date virus checker on this file, and any other file you import from an outside source. Make sure your virus checker’s data files are up to date, too. Keep in mind: the version of this file you are reading may be different from the version we checked! Confidentiality: We respect your copyright, and do not distribute your presentation before the conference. However, we cannot promise strict confidentiality of your presentation before the conference, because others have read access to our FTP sites. Do not include confidential information in your presentation. Test Slide: A test slide is included as a “hidden slide” after the end of this presentation. If you want to do a trial projection, ensure that your projector projects the entire slide, and that aspect ratios are correct. We will use the same test slide at the conference for setup of our projection equipment. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Test Basics Likely defects
Depend on the circuit, layout, process control Difficult to obtain Simplify the problem by targeting only Logical Faults Fault Model Physical Defects Logical Faults View it as a slide show first. It will highlight important aspects of your presentation, and give you an example of a presentation that lives up to ITC presentation standards and guidelines. Virus checker: When we created this presentation guide it contained no known viruses. This file was checked by McAfee VShield 4.x software before being distributed to authors. You should use a good, up to date virus checker on this file, and any other file you import from an outside source. Make sure your virus checker’s data files are up to date, too. Keep in mind: the version of this file you are reading may be different from the version we checked! Confidentiality: We respect your copyright, and do not distribute your presentation before the conference. However, we cannot promise strict confidentiality of your presentation before the conference, because others have read access to our FTP sites. Do not include confidential information in your presentation. Test Slide: A test slide is included as a “hidden slide” after the end of this presentation. If you want to do a trial projection, ensure that your projector projects the entire slide, and that aspect ratios are correct. We will use the same test slide at the conference for setup of our projection equipment. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

The Stuck-at Fault Model
Assumes defects cause a signal line to be permanently stuck high or stuck low s-a Stuck-at 0 s-a Stuck-at 1 How good is this model? What does it buy us? View it as a slide show first. It will highlight important aspects of your presentation, and give you an example of a presentation that lives up to ITC presentation standards and guidelines. Virus checker: When we created this presentation guide it contained no known viruses. This file was checked by McAfee VShield 4.x software before being distributed to authors. You should use a good, up to date virus checker on this file, and any other file you import from an outside source. Make sure your virus checker’s data files are up to date, too. Keep in mind: the version of this file you are reading may be different from the version we checked! Confidentiality: We respect your copyright, and do not distribute your presentation before the conference. However, we cannot promise strict confidentiality of your presentation before the conference, because others have read access to our FTP sites. Do not include confidential information in your presentation. Test Slide: A test slide is included as a “hidden slide” after the end of this presentation. If you want to do a trial projection, ensure that your projector projects the entire slide, and that aspect ratios are correct. We will use the same test slide at the conference for setup of our projection equipment. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Stuck-at Test for NAND4 Fault List:
Y A B C D Fault List: Possible Faults {A/0, A/1, B/0, B/1, C/0, C/1, D/0, D/1, Y/0, Y/1} Test Faults Detected A B C D A/0, B/0, C/0, D/0, Y/1 A/1, Y/0 B/1, Y/0 C/1, Y/0 D/1, Y/0 View it as a slide show first. It will highlight important aspects of your presentation, and give you an example of a presentation that lives up to ITC presentation standards and guidelines. Virus checker: When we created this presentation guide it contained no known viruses. This file was checked by McAfee VShield 4.x software before being distributed to authors. You should use a good, up to date virus checker on this file, and any other file you import from an outside source. Make sure your virus checker’s data files are up to date, too. Keep in mind: the version of this file you are reading may be different from the version we checked! Confidentiality: We respect your copyright, and do not distribute your presentation before the conference. However, we cannot promise strict confidentiality of your presentation before the conference, because others have read access to our FTP sites. Do not include confidential information in your presentation. Test Slide: A test slide is included as a “hidden slide” after the end of this presentation. If you want to do a trial projection, ensure that your projector projects the entire slide, and that aspect ratios are correct. We will use the same test slide at the conference for setup of our projection equipment. Test Set size = n+1 not 2n Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Stuck-at-fault Model Was reasonable for Bipolar technologies and NMOS
View it as a slide show first. It will highlight important aspects of your presentation, and give you an example of a presentation that lives up to ITC presentation standards and guidelines. Virus checker: When we created this presentation guide it contained no known viruses. This file was checked by McAfee VShield 4.x software before being distributed to authors. You should use a good, up to date virus checker on this file, and any other file you import from an outside source. Make sure your virus checker’s data files are up to date, too. Keep in mind: the version of this file you are reading may be different from the version we checked! Confidentiality: We respect your copyright, and do not distribute your presentation before the conference. However, we cannot promise strict confidentiality of your presentation before the conference, because others have read access to our FTP sites. Do not include confidential information in your presentation. Test Slide: A test slide is included as a “hidden slide” after the end of this presentation. If you want to do a trial projection, ensure that your projector projects the entire slide, and that aspect ratios are correct. We will use the same test slide at the conference for setup of our projection equipment. Was reasonable for Bipolar technologies and NMOS Less good for CMOS Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

CMOS Stuck-open A combinational circuit can become sequential
View it as a slide show first. It will highlight important aspects of your presentation, and give you an example of a presentation that lives up to ITC presentation standards and guidelines. Virus checker: When we created this presentation guide it contained no known viruses. This file was checked by McAfee VShield 4.x software before being distributed to authors. You should use a good, up to date virus checker on this file, and any other file you import from an outside source. Make sure your virus checker’s data files are up to date, too. Keep in mind: the version of this file you are reading may be different from the version we checked! Confidentiality: We respect your copyright, and do not distribute your presentation before the conference. However, we cannot promise strict confidentiality of your presentation before the conference, because others have read access to our FTP sites. Do not include confidential information in your presentation. Test Slide: A test slide is included as a “hidden slide” after the end of this presentation. If you want to do a trial projection, ensure that your projector projects the entire slide, and that aspect ratios are correct. We will use the same test slide at the conference for setup of our projection equipment. A combinational circuit can become sequential Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Test Generation for Combinational Circuits
Conceptually simple: Derive a truth table for the fault free circuit Derive a truth table for the faulty circuit Select a row with differing outputs View it as a slide show first. It will highlight important aspects of your presentation, and give you an example of a presentation that lives up to ITC presentation standards and guidelines. Virus checker: When we created this presentation guide it contained no known viruses. This file was checked by McAfee VShield 4.x software before being distributed to authors. You should use a good, up to date virus checker on this file, and any other file you import from an outside source. Make sure your virus checker’s data files are up to date, too. Keep in mind: the version of this file you are reading may be different from the version we checked! Confidentiality: We respect your copyright, and do not distribute your presentation before the conference. However, we cannot promise strict confidentiality of your presentation before the conference, because others have read access to our FTP sites. Do not include confidential information in your presentation. Test Slide: A test slide is included as a “hidden slide” after the end of this presentation. If you want to do a trial projection, ensure that your projector projects the entire slide, and that aspect ratios are correct. We will use the same test slide at the conference for setup of our projection equipment. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Generating a Test Set Essential Tests {010, 100, 110}
Minimal Test Set (not unique) {010, 100, 110, 001} View it as a slide show first. It will highlight important aspects of your presentation, and give you an example of a presentation that lives up to ITC presentation standards and guidelines. Virus checker: When we created this presentation guide it contained no known viruses. This file was checked by McAfee VShield 4.x software before being distributed to authors. You should use a good, up to date virus checker on this file, and any other file you import from an outside source. Make sure your virus checker’s data files are up to date, too. Keep in mind: the version of this file you are reading may be different from the version we checked! Confidentiality: We respect your copyright, and do not distribute your presentation before the conference. However, we cannot promise strict confidentiality of your presentation before the conference, because others have read access to our FTP sites. Do not include confidential information in your presentation. Test Slide: A test slide is included as a “hidden slide” after the end of this presentation. If you want to do a trial projection, ensure that your projector projects the entire slide, and that aspect ratios are correct. We will use the same test slide at the conference for setup of our projection equipment. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Generating a Test Set Such a tabular method is completely impractical because of the exponential growth in table size with number of inputs Picking a minimal complete test set from such a table is also a NP Complete problem We use the circuit structure to generate the test set in practice View it as a slide show first. It will highlight important aspects of your presentation, and give you an example of a presentation that lives up to ITC presentation standards and guidelines. Virus checker: When we created this presentation guide it contained no known viruses. This file was checked by McAfee VShield 4.x software before being distributed to authors. You should use a good, up to date virus checker on this file, and any other file you import from an outside source. Make sure your virus checker’s data files are up to date, too. Keep in mind: the version of this file you are reading may be different from the version we checked! Confidentiality: We respect your copyright, and do not distribute your presentation before the conference. However, we cannot promise strict confidentiality of your presentation before the conference, because others have read access to our FTP sites. Do not include confidential information in your presentation. Test Slide: A test slide is included as a “hidden slide” after the end of this presentation. If you want to do a trial projection, ensure that your projector projects the entire slide, and that aspect ratios are correct. We will use the same test slide at the conference for setup of our projection equipment. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Single Stuck-at Fault Three properties define a single stuck-at fault
Only one line is faulty The faulty line is permanently set to 0 or 1 The fault can be at an input or output of a gate Example: XOR circuit has 12 fault sites ( ● ) and 24 single stuck-at faults Faulty circuit value s-a-0 Good circuit value c j 0(1) a d 1 g 1(0) h z z i e 1 b 1 k f Test vector for h s-a-0 fault Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Fault Collapsing Number of fault sites in a Boolean gate circuit
N = #PI + #gates + # (fanout branches) Number of faults to be tested is 2N (Size of the initial fault list) Fault collapsing attempts to reduce the size of the fault list such than any test set that tests for all faults on this collapsed fault list will also test for all 2N faults in the circuit Fault collapsing exploits fault equivalence and fault dominance Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Fault Equivalence Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2. If faults f1 and f2 are equivalent then the corresponding faulty functions are identical. Equivalence collapsing: All single faults of a logic circuit can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Equivalence Rules sa0 sa0 sa1 sa1 sa0 sa1 sa0 sa1 WIRE sa0 sa1 sa0 sa1
AND OR sa0 sa1 sa0 sa1 sa0 sa1 NOT sa1 sa0 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 NAND NOR sa1 sa0 sa0 sa1 sa0 sa1 sa1 sa0 sa1 FANOUT Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Fault Dominance If all tests of some fault F1 detect another fault F2, then F2 is said to dominate F1. Dominance collapsing: If fault F2 dominates F1, then F2 is removed from the fault list. When dominance fault collapsing is used, it is sufficient to consider only the input faults of Boolean gates. See the next example. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Dominance Example All tests of F2 F1 s-a-1 001 F2 F2 110 010 000 s-a-1
000 101 100 s-a-1 F2 F2 s-a-1 011 Only test of F1 s-a-1 s-a-1 s-a-1 s-a-0 A dominance collapsed fault set Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Checkpoints Primary inputs and fanout branches of a combinational circuit are called checkpoints. Checkpoint theorem: A test set that detects all single (multiple) stuck-at faults on all checkpoints of a combinational circuit, also detects all single (multiple) stuck-at faults in that circuit. Total fault sites = 16 Checkpoints ( ● ) = 10 Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Multiple Stuck-at Faults
A multiple stuck-at fault means that any set of lines is stuck-at some combination of (0,1) values. The total number of single and multiple stuck-at faults in a circuit with k single fault sites is 3k-1. A single fault test can fail to detect the target fault if another fault is also present, however, such masking of one fault by another is rare. Statistically, single fault tests cover a very large number of multiple faults. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Summary Fault models are analyzable approximations of defects and are essential for a test methodology. For digital logic single stuck-at fault model offers best advantage of tools and experience. Many other faults (bridging, stuck-open and multiple stuck-at) are largely covered by stuck-at fault tests. Stuck-short and delay faults and technology-dependent faults require special tests. Memory and analog circuits need other specialized fault models and tests. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Simulation What is simulation? Design verification Circuit modeling
True-value simulation algorithms Compiled-code simulation Event-driven simulation Summary Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Simulation Defined Definition: Simulation refers to modeling of a design, its function and performance. A software simulator is a computer program; an emulator is a hardware simulator. Simulation is used for design verification: Validate assumptions Verify logic Verify performance (timing) Types of simulation: Logic or switch level Timing Circuit Fault Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Simulation for Verification
Specification Synthesis Response analysis Design changes Design (netlist) Computed responses True-value simulation Input stimuli Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Modeling for Simulation
Modules, blocks or components described by Input/output (I/O) function Delays associated with I/O signals Examples: binary adder, Boolean gates, FET, resistors and capacitors Interconnects represent ideal signal carriers, or ideal electrical conductors Netlist: a format (or language) that describes a design as an interconnection of modules. Netlist may use hierarchy. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Example: A Full-Adder HA HA1 HA2 HA; inputs: a, b; outputs: c, f;
AND: A1, (a, b), (c); AND: A2, (d, e), (f); OR: O1, (a, b), (d); NOT: N1, (c), (e); Half-adder HA1 HA2 A B C D E F Sum Carry FA; inputs: A, B, C; outputs: Carry, Sum; HA: HA1, (A, B), (D, E); HA: HA2, (E, C), (F, Sum); OR: O2, (D, F), (Carry); Full-adder Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Logic Model of MOS Circuit
VDD pMOS FETs a Da Dc c a Ca b Db c Cc b Da and Db are interconnect or propagation delays Dc is inertial delay of gate Cb nMOS FETs Ca , Cb and Cc are parasitic capacitances Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Options for Inertial Delay (simulation of a NAND gate)
Transient region a Inputs b c (CMOS) c (zero delay) c (unit delay) Logic simulation X c (multiple delay) rise=5, fall=5 Unknown (X) c (minmax delay) min =2, max =5 5 Time units Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Signal States Two-states (0, 1) can be used for purely combinational logic with zero-delay. Three-states (0, 1, X) are essential for timing hazards and for sequential logic initialization. Four-states (0, 1, X, Z) are essential for MOS devices. See example below. Analog signals are used for exact timing of digital logic and for analog circuits. Z (hold previous value) Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Modeling Levels Modeling level Function, behavior, RTL Logic Switch
Timing Circuit Circuit description Programming language-like HDL Connectivity of Boolean gates, flip-flops and transistors Transistor size and connectivity, node capacitances Transistor technology data, connectivity, Tech. Data, active/ passive component connectivity Signal values 0, 1 0, 1, X and Z and X Analog voltage voltage, current Timing Clock boundary Zero-delay unit-delay, multiple- delay Fine-grain timing Continuous time Application Architectural and functional verification Logic and test Timing Digital timing and analog circuit Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

True-Value Simulation Algorithms
Compiled-code simulation Applicable to zero-delay combinational logic Also used for cycle-accurate synchronous sequential circuits for logic verification Efficient for highly active circuits, but inefficient for low-activity circuits High-level (e.g., C language) models can be used Event-driven simulation Only gates or modules with input events are evaluated (event means a signal change) Delays can be accurately simulated for timing verification Efficient for low-activity circuits Can be extended for fault simulation Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Compiled-Code Algorithm
Step 1: Levelize combinational logic and encode in a compilable programming language Step 2: Initialize internal state variables (flip-flops) Step 3: For each input vector Set primary input variables Repeat (until steady-state or max. iterations) Execute compiled code Report or save computed variables Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Event-Driven Algorithm (Example)
Scheduled events c = 0 d = 1, e = 0 g = 0 f = 1 g = 1 Activity list d, e f, g g a =1 e =1 t = 0 1 2 3 4 5 6 7 8 2 c = g =1 2 2 d = 0 4 f =0 b =1 Time stack g 4 8 Time, t Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Efficiency of Event-Driven Simulator
Simulates events (value changes) only Speed up over compiled-code can be ten times or more; in large logic circuits about 0.1 to 10% gates become active for an input change Steady 0 0 → 1 event Steady 0 (no event) Large logic block without activity Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Summary Logic or true-value simulators are essential tools for design verification. Verification vectors and expected responses are generated (often manually) from specifications. A logic simulator can be implemented using either compiled-code or event-driven method. Per vector complexity of a logic simulator is approximately linear in circuit size. Modeling level determines the evaluation procedures used in the simulator. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Fault Simulation Problem and motivation Fault simulation algorithms
Serial Parallel Concurrent Random Fault Sampling Summary Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Problem and Motivation
Fault simulation Problem: Given A circuit A sequence of test vectors A fault model Determine Fault coverage - fraction (or percentage) of modeled faults detected by test vectors Set of undetected faults Motivation Determine test quality and in turn product quality Find undetected fault targets to improve tests Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Fault simulator in a VLSI Design Process
Verification input stimuli Verified design netlist Fault simulator Test vectors Modeled fault list Remove tested faults Test compactor Delete vectors Fault coverage ? Low Test generator Add vectors Adequate Stop Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Fault Simulation Scenario
Circuit model: mixed-level Mostly logic with some switch-level for high-impedance (Z) and bidirectional signals High-level models (memory, etc.) with pin faults Signal states: logic Two (0, 1) or three (0, 1, X) states for purely Boolean logic circuits Four states (0, 1, X, Z) for sequential MOS circuits Timing: Zero-delay for combinational and synchronous circuits Mostly unit-delay for circuits with feedback Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Fault Simulation Scenario (Continued)
Mostly single stuck-at faults Sometimes stuck-open, transition, and path-delay faults; analog circuit fault simulators are not yet in common use Equivalence fault collapsing of single stuck-at faults Fault-dropping -- a fault once detected is dropped from consideration as more vectors are simulated; fault-dropping may be suppressed for diagnosis Fault sampling -- a random sample of faults is simulated when the circuit is large Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Fault Simulation Algorithms
Serial Parallel Deductive* Concurrent Differential* * Not discussed; see M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000, Chapter 5. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Serial Algorithm Algorithm: Simulate fault-free circuit and save responses. Repeat following steps for each fault in the fault list: Modify netlist by injecting one fault Simulate modified netlist, vector by vector, comparing responses with saved responses If response differs, report fault detection and suspend simulation of remaining vectors Advantages: Easy to implement; needs only a true-value simulator, less memory Most faults, including analog faults, can be simulated Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Serial Algorithm (Cont.)
Disadvantage: Much repeated computation; CPU time prohibitive for VLSI circuits Alternative: Simulate many faults together Test vectors Fault-free circuit Comparator f1 detected? Circuit with fault f1 Comparator f2 detected? Circuit with fault f2 Comparator fn detected? Circuit with fault fn Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Parallel Fault Simulation
Compiled-code method; best with two-states (0,1) Exploits inherent bit-parallelism of logic operations on computer words Storage: one word per line for two-state simulation Multi-pass simulation: Each pass simulates w-1 new faults, where w is the machine word length Speed up over serial method ~ w-1 Not suitable for circuits with timing-critical and non-Boolean logic Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Parallel Fault Sim. Example
Bit 0: fault-free circuit Bit 1: circuit with c s-a-0 Bit 2: circuit with f s-a-1 c s-a-0 detected a b e c s-a-0 g d f s-a-1 Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Concurrent Fault Simulation
Event-driven simulation of fault-free circuit and only those parts of the faulty circuit that differ in signal states from the fault-free circuit. A list per gate containing copies of the gate from all faulty circuits in which this gate differs. List element contains fault ID, gate input and output values and internal states, if any. All events of fault-free and all faulty circuits are implicitly simulated. Faults can be simulated in any modeling style or detail supported in true-value simulation (offers most flexibility.) Faster than other methods, but uses most memory. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Conc. Fault Sim. Example a0 b0 c0 e0 a0 b0 c0 e0 b0 d0 f1 g0 f1 d0 a e
1 1 1 1 1 a 1 1 1 e b 1 c 1 1 g 1 a0 b0 c0 e0 d f 1 1 1 1 b0 d0 f1 g0 1 f1 d0 1 1 Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Fault Sampling A randomly selected subset (sample) of faults is simulated. Measured coverage in the sample is used to estimate fault coverage in the entire circuit. Advantage: Saving in computing resources (CPU time and memory.) Disadvantage: Limited data on undetected faults. In practice, if a set of few thousand faults is randomly selected, the simulation gives a reasonably accurate estimate of the true fault coverage, irrespective of the circuit size. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Motivation for Sampling
Complexity of fault simulation depends on: Number of gates Number of faults Number of vectors Complexity of fault simulation with fault sampling depends on: Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Random Sampling Model Detected Undetected fault fault All faults with
a fixed but unknown coverage Random picking Np = total number of faults (population size) C = fault coverage (unknown) Ns = sample size Ns << Np c = sample coverage (a random variable) Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Probability Density of Sample Coverage, c
(x ─ C )2 ─ ───── σ 2 p (x ) = Prob(x ≤ c ≤ x +dx ) = ─────── e σ (2 π) 1/2 C (1 ─ C) Variance, σ 2 = ────── Ns Sampling error σ σ p (x ) Mean = C x C -3σ C x C +3σ 1.0 Sample coverage Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Sampling Error Bounds C (1 - C ) | x - C | = 3 [ ─────── ] 1/2 Ns
Solving the quadratic equation for C, we get the 3-sigma (99.7% confidence) estimate: 4.5 C 3σ = x ± ─── [ Ns x (1 ─ x )]1/2 Ns Where Ns is sample size and x is the measured fault coverage in the sample. Example: A circuit with 39,096 faults has an actual fault coverage of 87.1%. The measured coverage in a random sample of 1,000 faults is 88.7%. The above formula gives an estimate of 88.7% ± 3%. CPU time for sample simulation was about 10% of that for all faults. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Summary Fault simulator is an essential tool for test development.
Concurrent fault simulation algorithm offers the best choice. For restricted class of circuits (combinational or synchronous sequential and with only Boolean primitives), differential algorithm can provide better speed and memory efficiency. For large circuits, the accuracy of random fault sampling only depends on the sample size (1,000 to 2,000 faults) and not on the circuit size. The method has significant advantages in reducing CPU time and memory needs of the simulator. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Testability Measures Definition Controllability and observability
SCOAP measures Combinational circuits Sequential circuits Summary Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

What are Testability Measures?
Approximate measures of: Difficulty of setting internal circuit lines to 0 or 1 from primary inputs. Difficulty of observing internal circuit lines at primary outputs. Applications: Analysis of difficulty of testing internal circuit parts – redesign or add special test hardware. Guidance for algorithms computing test patterns – avoid using hard-to-control lines. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Testability Analysis Determines testability measures
Involves Circuit Topological analysis, but no test vectors (static analysis) and no search algorithm. Linear computational complexity Otherwise, analysis is pointless – might as well use automatic test-pattern generation and calculate: Exact fault coverage Exact test vectors Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

SCOAP Measures SCOAP – Sandia Controllability and Observability Analysis Program Combinational measures: CC0 – Difficulty of setting circuit line to logic 0 CC1 – Difficulty of setting circuit line to logic 1 CO – Difficulty of observing a circuit line Sequential measures – analogous: SC0 SC1 SO Ref.: L. H. Goldstein, “Controllability/Observability Analysis of Digital Circuits,” IEEE Trans. CAS, vol. CAS-26, no. 9. pp. 685 – 693, Sep Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Range of SCOAP Measures
Controllabilities – 1 (easiest) to infinity (hardest) Observabilities – 0 (easiest) to infinity (hardest) Combinational measures: Roughly proportional to number of circuit lines that must be set to control or observe given line. Sequential measures: Roughly proportional to number of times flip-flops must be clocked to control or observe given line. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Combinational Controllability
Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Controllability Formulas (Continued)

Combinational Observability
To observe a gate input: Observe output and make other input values non-controlling. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Observability Formulas (Continued)
Fanout stem: Observe through branch with best observability. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Comb. Controllability Circled numbers give level number. (CC0, CC1)

Controllability Through Level 2

Final Combinational Controllability

Combinational Observability for Level 1
Number in square box is level from primary outputs (POs). (CC0, CC1) CO Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Combinational Observabilities for Level 2

Final Combinational Observabilities

Sequential Measures (Comparison)
Combinational Increment CC0, CC1, CO whenever you pass through a gate, either forward or backward. Sequential Increment SC0, SC1, SO only when you pass through a flip-flop, either forward or backward. Both Must iterate on feedback loops until controllabilities stabilize. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

D Flip-Flop Equations Assume a synchronous RESET line.
CC1 (Q) = CC1 (D) + CC1 (C) + CC0 (C) + CC0 (RESET) SC1 (Q) = SC1 (D) + SC1 (C) + SC0 (C) + SC0 (RESET) + 1 CC0 (Q) = min [CC1 (RESET) + CC1 (C) + CC0 (C), CC0 (D) + CC1 (C) + CC0 (C)] SC0 (Q) is analogous CO (D) = CO (Q) + CC1 (C) + CC0 (C) + CC0 SO (D) is analogous Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

D Flip-Flop Clock and Reset
CO (RESET) = CO (Q) + CC1 (Q) + CC1 (RESET) + CC1 (C) + CC0 (C) SO (RESET) is analogous Three ways to observe the clock line: Set Q to 1 and clock in a 0 from D Set the flip-flop and then reset it Reset the flip-flop and clock in a 1 from D CO (C) = min [ CO (Q) + CC1 (Q) + CC0 (D) + CC1 (C) + CC0 (C), CO (Q) + CC1 (Q) + CC1 (RESET) + CO (Q) + CC0 (Q) + CC0 (RESET) + CC1 (D) + CC1 (C) + CC0 (C)] SO (C) is analogous Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Testability Computation
For all PIs, CC0 = CC1 = 1 and SC0 = SC1 = 0 For all other nodes, CC0 = CC1 = SC0 = SC1 = ∞ Go from PIs to POs, using CC and SC equations to get controllabilities -- Iterate on loops until SC stabilizes -- convergence is guaranteed. Set CO = SO = 0 for POs, ∞ for all other lines. Work from POs to PIs, Use CO, SO, and controllabilities to get observabilities. Fanout stem (CO, SO) = min branch (CO, SO) If a CC or SC (CO or SO) is ∞ , that node is uncontrollable (unobservable). Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Sequential Example Initialization

Stable Sequential Measures

Final Sequential Observabilities

Summary Testability measures are approximate measures of:
Difficulty of setting circuit lines to 0 or 1 Difficulty of observing internal circuit lines Applications: Analysis of difficulty of testing internal circuit parts Redesign circuit hardware or add special test hardware where measures show poor controllability or observability. Guidance for algorithms computing test patterns – avoid using hard-to-control lines Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Exercise 1 Answer Counting two faults on each line,
Total number of faults = 2 × (#PI + #gates + #fanout branches) = 2 × ( ) = 12 s-a-0 s-a-1 s-a-0 s-a-1 s-a-0 s-a-1 s-a-0 s-a-1 s-a-0 s-a-1 s-a-0 s-a-1 Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Exercise 2 For the circuit shown above
Using the parallel fault simulation algorithm, determine which of the four primary input faults are detectable by the test 00. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Exercise 2: Answer ■ Parallel fault simulation of four PI faults is illustrated below. Fault PI2 s-a-1 is detected by the 00 test input. PI1=0 PI2=0 No fault PI1 s-a-0 PI1 s-a-1 PI2 s-a-0 PI2 s-a-1 PI2 s-a-1 detected Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Determine SCOAP testability measures. Using the sum of controllability and observability as a measure of testability, list the most difficult to test faults. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

■ SCOAP testability measures, (CC0, CC1) CO, are shown below:
Exercise 3: Answer ■ SCOAP testability measures, (CC0, CC1) CO, are shown below: s-a-0 s-a-1 (1,1) 4 (2,3) 2 (4,2) 0 (1,1) 4 s-a-0 (1,1) 3 (1,1) 3 s-a-0 s-a-1 Five faults, shown in the figure, have the highest testability measure of 5. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 1)

Combinational ATPG ATPG problem Example Algorithms
Multi-valued algebra D-algorithm Podem Other algorithms ATPG system Summary Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

ATPG Problem ATPG: Automatic test pattern generation Given Find
A circuit (usually at gate-level) A fault model (usually stuck-at type) Find A set of input vectors to detect all modeled faults. Core solution: Find a test vector for a given fault. Combine the “core solution” with a fault simulator into an ATPG system. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

What is a Test? Fault activation Fault effect X Combinational circuit
1 Combinational circuit 1/0 1/0 Primary inputs (PI) Primary outputs (PO) Path sensitization Stuck-at-0 fault Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Multiple-Valued Algebras
Symbol D 1 X G0 G1 F0 F1 Alternative Representation 1/0 0/1 0/0 1/1 X/X 0/X 1/X X/0 X/1 Fault-free circuit 1 X Faulty Circuit 1 X Roth’s Algebra Muth’s Additions Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

An ATPG Example Fault activation Path sensitization Line justification
1 D Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

ATPG Example (Cont.) Fault activation Path sensitization
Line justification Path from fault site to a primary output D D 1 D D Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

D-Algorithm (Roth 1967) Use D-algebra Activate fault
Place a D or D at fault site Justify all signals Repeatedly propagate D-chain toward POs through a gate Backtrack if A conflict occurs, or All D-chains die Stop when D or D at a PO, i.e., test found, or Search exhausted, no test possible Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Example: Fault A sa0 Step 1 – Fault activation – Set A = 1 D 1 D
D-frontier = {e, h} Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Example Continued Step 2 – D-Drive – Set f = 0 D 1 D D
D 1 D D Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Example Continued Step 3 – D-Drive – Set k = 1 1 D D 1 D D

Example Continued Step 4 – Consistency – Set g = 1 1 1 D D 1 D D

Example Continued Step 5 – Consistency – f = 0 Already set 1 1 D D 1 D

Example Continued Step 6 – Consistency – Set c = 0, Set e = 0 1 1 D D
D D 1 D D Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Example: Test Found X 1 1 D D 1 D D Step 7 – Consistency – Set B = 0
Test: A = 1, B = 0, C = 0, D = X X 1 1 D D 1 D D Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Podem (Goel, 1981) Podem: Path oriented decision making
Step 1: Define an objective (fault activation, D-drive, or line justification) Step 2: Backtrace from site of objective to PIs (use testability measures guidance) to determine a value for a PI Step 3: Simulate logic with new PI value If objective not accomplished but is possible, then continue backtrace to another PI (step 2) If objective accomplished and test not found, then define new objective (step 1) If objective becomes impossible, try alternative backtrace (step 2) Use X-PATH-CHECK to test whether D-frontier still there – a path of X’s from a D-frontier to a PO must exist. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Podem Example 3. Logic simulation for A=0 2. Backtrace “A=0”
1. Objective “0” S-a-1 (9, 2) 4. Objective possible but not accomplished Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Podem Example (Cont.) 6. Logic simulation for A=0, B=0
5. Backtrace “B=0” 1. Objective “0” S-a-1 (9, 2) 7. Objective possible but not accomplished Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Podem Example (Cont.) 9. Logic simulation for E=0 1. Objective “0”
8. Backtrace “E=0” 1. Objective “0” S-a-1 (9, 2) 10. Objective possible but not accomplished Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Podem Example (Cont.) 12. Logic simulation for D=0 1. Objective “0”
S-a-1 (9, 2) 13. Objective accomplished 11. Backtrace “D=0” Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

An ATPG System Random pattern generator Fault simulator yes Fault
coverage improved? Random patterns effective? Deterministic ATPG (D-alg. or Podem) Save patterns yes no no Stop if fault coverage goal achieved Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Summary Most combinational ATPG algorithms use D-algebra.
D-Algorithm is a complete algorithm: Finds a test, or Determines the fault to be redundant Complexity is exponential in circuit size Podem is also a complete algorithm: Works on primary inputs – search space is smaller than that of D-algorithm Exponential complexity, but several orders faster than D-algorithm More efficient algorithms available – FAN, Socrates, etc. See, M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000, Chapter 7. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Sequential ATPG A sequential circuit has memory in addition to combinational logic. Test for a fault in a sequential circuit is a sequence of vectors, which Initializes the circuit to a known state Activates the fault, and Propagates the fault effect to a primary output Methods of sequential circuit ATPG Time-frame expansion methods Simulation-based methods Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Example: A Serial Adder
An Bn 1 1 s-a-0 D 1 1 D X Cn Cn+1 X 1 Combinational logic Sn X FF Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Time-Frame Expansion An-1 Bn-1 Time-frame -1 An Bn Time-frame 0 Cn-1
s-a-0 D X s-a-0 D D 1 1 Cn-1 1 D X Cn 1 D 1 Cn+1 X 1 Combinational logic Combinational logic 1 Sn-1 Sn X D FF Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Concept of Time-Frames
If the test sequence for a single stuck-at fault contains n vectors, Replicate combinational logic block n times Place fault in each block Generate a test for the multiple stuck-at fault using combinational ATPG with 9-valued logic Vector -n+1 Vector -1 Vector 0 Fault Unknown or given Init. state Time- frame -n+1 State variables Time- frame -1 Time- frame Next state Comb. block PO -n+1 PO -1 PO 0 Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Example for Logic Systems
FF1 B A FF2 s-a-1 Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Five-Valued Logic (Roth) 0,1, D, D, X
A s-a-1 s-a-1 D D X X X FF1 FF1 X D D FF2 FF2 B X B X Time-frame -1 Time-frame 0 Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Nine-Valued Logic (Muth) 0,1, 1/0, 0/1, 1/X, 0/X, X/0, X/1, X
A X s-a-1 s-a-1 0/1 X/1 X 0/X 0/X FF1 FF1 X 0/1 X/1 FF2 FF2 B X B 0/1 Time-frame -1 Time-frame 0 Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Implementation of ATPG
Select a PO for fault detection based on drivability analysis. Place a logic value, 1/0 or 0/1, depending on fault type and number of inversions. Justify the output value from PIs, considering all necessary paths and adding backward time-frames. If justification is impossible, then use drivability to select another PO and repeat justification. If the procedure fails for all reachable POs, then the fault is untestable. If 1/0 or 0/1 cannot be justified at any PO, but 1/X or 0/X can be justified, the the fault is potentially detectable. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Drivability Example (11, 16) (10, 15) (22, 17) (10, 16) d(0/1) =
8 s-a-1 d(0/1) = 4 d(1/0) = d(0/1) = d(1/0) = 20 8 8 (5, 9) (4, 4) (17, 11) d(0/1) = 9 d(1/0) = (6, 10) (CC0, CC1) = (6, 4) d(0/1) = 120 d(1/0) = 27 8 FF d(0/1) = 109 d(1/0) = 8 CC0 and CC1 are SCOAP combinational controllabilities d(0/1) and d(1/0) of a line are effort measures for driving a specific fault effect to that line Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Complexity of ATPG Synchronous circuit – All flip-flops controlled by clocks; PI and PO synchronized with clock: Cycle-free circuit – No feedback among flip-flops: Test generation for a fault needs no more than dseq + 1 time-frames, where dseq is the sequential depth. Cyclic circuit – Contains feedback among flip-flops: May need 9Nff time-frames, where Nff is the number of flip-flops. Asynchronous circuit – Higher complexity! Smax Time- Frame max-1 Time- Frame max-2 S3 Time- Frame -2 S2 Time- Frame -1 S1 Time- Frame S0 max = Number of distinct vectors with 9-valued elements = 9Nff Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Cycle-Free Circuits Characterized by absence of cycles among flip-flops and a sequential depth, dseq. dseq is the maximum number of flip-flops on any path between PI and PO. Both good and faulty circuits are initializable. Test sequence length for a fault is bounded by dseq + 1. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

A Cycle-Free Circuit Example
2 All faults are testable in this circuit. F3 F1 3 Level = 1 F1 F2 F3 Level = 1 2 3 s - graph dseq = 3 Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

A Cyclic Circuit Example
Modulo-3 counter Z CNT F2 F1 s - graph F1 F2 Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Modulo-3 Counter Cyclic structure – Sequential depth is undefined.
Circuit is not initializable. No tests can be generated for any stuck-at fault. After expanding the circuit to 9Nff = 81, or fewer, time-frames ATPG program calls any given target fault untestable. Circuit can only be functionally tested by multiple observations. Functional tests, when simulated, give no fault coverage. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Adding Initializing Hardware
Initializable modulo-3 counter Z CNT F2 F1 s-a-0 s-a-1 CLR s-a-1 s-a-1 Untestable fault Potentially detectable faults s - graph F1 F2 Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Benchmark Circuits Circuit PI PO FF Gates Structure Seq. depth
Total faults Detected faults Potentially detected faults Untestable faults Abandoned faults Fault coverage (%) Fault efficiency (%) Max. sequence length Total test vectors Gentest CPU s (Sparc 2) s1196 14 18 529 Cycle-free 4 1242 1239 3 99.8 100.0 313 10 s1238 14 18 508 Cycle-free 4 1355 1283 72 94.7 100.0 3 308 15 s1488 8 19 6 653 Cyclic -- 1486 1384 2 26 76 93.1 94.8 24 525 19941 s1494 8 19 6 647 Cyclic -- 1506 1379 2 30 97 91.6 93.4 28 559 19183 Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Summary Combinational ATPG algorithms are extended:
Time-frame expansion unrolls time as combinational array Nine-valued logic system Justification via backward time Cycle-free circuits: Require at most dseq + 1 time-frames Always initializable Cyclic circuits: May need 9Nff time-frames Circuit must be initializable Partial scan can make circuit cycle-free Asynchronous circuits: Not discussed See, M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000, Chapter 8. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

s-a-1 For the circuit shown above Derive a test for the stuck-at-1 fault at the output of the AND gate. Using the parallel fault simulation algorithm, determine which of the four primary input faults are detectable by the test derived above. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Exercise 4: Answer Continued
■ Parallel fault simulation of four PI faults is illustrated below. Fault PI2 s-a-1 is detected by the 00 test input. PI1=0 PI2=0 No fault PI1 s-a-0 PI1 s-a-1 PI2 s-a-0 PI2 s-a-1 PI2 s-a-1 detected Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Delay Test Definition A circuit that passes delay test must produce correct outputs when inputs are applied and outputs observed with specified timing. For a combinational or synchronous sequential circuit, delay test verifies the limits of delay in combinational logic. Delay test problem for asynchronous circuits is complex and not well understood. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Digital Circuit Timing
Input Signal changes Output Observation instant Transient region Comb. logic Inputs Synchronized With clock Outputs time Clock period Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Circuit Delays Switching or inertial delay is the interval between input change and output change of a gate: Depends on input capacitance, device (transistor) characteristics and output capacitance of gate. Also depends on input rise or fall times and states of other inputs (second-order effects). Approximation: fixed rise and fall delays (or min-max delay range, or single fixed delay) for gate output. Propagation or interconnect delay is the time a transition takes to travel between gates: Depends on transmission line effects (distributed R, L, C parameters, length and loading) of routing paths. Approximation: modeled as lumped delays for gate inputs. See logic simulation for timing models. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Event Propagation Delays
Single lumped inertial delay modeled for each gate PI transitions assumed to occur without time skew Path P1 1 3 1 2 4 6 P2 1 2 3 P3 5 2 Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Delay Test Generation Problem: Variations in CMOS Delays
Switching delays in CMOS greatly depend on the off path signals and internal circuit state Hard to find <V1, V2> to ensure worst case conditions for signal propagation along a path. Often this worst case test vector pair can be different for the same circuit depending on fabrication parameters A B C output A B C Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Circuit Outputs Each path can potentially produce one signal transition at the output. The location of an output transition in time is determined by the delay of the path. Clock period Final value Initial value Fast transitions Slow transitions Initial value Final value time Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

The Transition Delay Fault (TDF) model
Assumes a single localized gross delay fault at some node Faulty node is either slow-to-rise or slow-to- fall For an N node circuit, 2N faults in the fault list Tested by 2-vector test <V1, V2> where the vector pair is selected to cause a rising (falling) transition at the node to test for a slow-to-rise (slow-to-fall) fault; also V2 is a stuck-at-0 (stuck-at-1) test for the node Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Singly-Testable Paths (Non-Robust Test)
The delay of a target path is tested if the test propagates a transition via path to a path destination. Delay test is a combinational vector-pair, V1,V2, that: Produces a transition at path input. Produces static sensitization – All off-path inputs assume non-controlling states in V2. don’t care Off-path inputs V1 V2 V1 V2 Target path Static sensitization guarantees a test when the target path is the only faulty path. The test is, therefore, called non-robust. It is a test with minimal restriction. A path with no such test is a false path. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Robust Test A robust test guarantees the detection of a delay fault of the target path, irrespective of delay faults on other paths. A robust test is a combinational vector-pair, V1, V2, that satisfies following conditions: Produce real events (different steady-state values for V1 and V2) on all on-path signals. All on-path signals must have controlling events arriving via the target path. A robust test is also a non-robust test. Concept of robust test is general – robust tests for other fault models can be defined. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Robust Test Conditions
Real events on target path. Controlling events via target path. V1 V2 V1 V2 V1 V2 V1 V2 U0 U1 U0 U1 U0/F0 U0/F0 U1/R1 U1/R1 V1 V2 V1 V2 S1 S0 S1 S0 U0/F0 U0/F0 U1/R1 U1/R1 Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

A Five-Valued Algebra Signal States: S0, U0 (F0), S1, U1 (R1), XX.
On-path signals: F0 and R1. Off-path signals: F0=U0 and R1=U1. Input 1 Input 1 AND S0 U0 S1 U1 XX S0 S0 S0 S0 S0 S0 U0 S0 U0 U0 U0 U0 S1 S0 U0 S1 U1 XX U1 S0 U0 U1 U1 XX XX S0 U0 XX XX XX S0 U0 S1 U1 XX S0 S0 U0 S1 U1 XX U0 U0 U0 S1 U1 XX S1 S1 S1 S1 S1 S1 U1 U1 U1 S1 U1 U1 XX XX XX S1 U1 XX OR Input 2 Input 2 Input S0 U0 S1 U1 XX S1 U1 S0 U0 XX Ref.: Lin-Reddy IEEETCAD-87 NOT Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Robust Test Generation
Test for ↓ P3 – falling transition through path P3: Steps A through E E. Set input of AND gate to S0 to justify S0 at output XX S0 S0 U0 D. Change off-path input to S0 to Propagate R1 through OR gate C. F0 interpreted as U0; propagates through AND gate U0 R1 A. Place F0 at path origin Path P3 F0 XX F0 R1 U0 Robust Test: S0, F0, U0 B. Propagate F0 through OR gate; also propagates as R1 through NOT gate Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Non-Robust Test Generation
Fault ↑ P2 – rising transition through path P2 has no robust test. C. Set input of AND gate to propagate R1 to output D. R1 non-robustly propagates through OR gate since off- path input is not S0 XX U1 R1 R1 Path P2 U1 A. Place R1 at path origin R1 R1 U1 U0 Non-robust test requires Static sensitization: S0=U0, S1=U1 XX U0 B. Propagate R1 through OR gate; interpreted as U1 on off-path signal; propagates as U0 through NOT gate Non-robust test: U1, R1, U0 Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Path-Delay Faults (PDF)
Two PDFs (rising and falling transitions) for each physical path. Total number of paths is an exponential function of gates. Critical paths, identified by static timing analysis (e.g., Primetime from Synopsys), must be tested. PDF tests are delay-independent. Robust tests are preferred, but some paths have only non-robust tests. Three types of PDFs (Gharaybeh, et al., JETTA (11), 1997): Singly-testable PDF – has a non-robust or robust test. Multiply-testable PDF – a set of singly untestable faults that has a non-robust or robust test. Also known as functionally testable PDF. Untestable PDF – a PDF that is neither singly nor multiply testable. A singly-testable PDF has at least one single-input change (SIC) non-robust test. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Other Delay Fault Models
Segment-delay fault – A segment of an I/O path is assumed to have large delay such that all paths containing the segment become faulty. Transition fault – A segment-delay fault with segment of unit length (single gate): Two faults per gate; slow-to-rise and slow-to-fall. Tests are similar to stuck-at fault tests. For example, a line is initialized to 0 and then tested for s-a-0 fault to detect slow-to-rise transition fault. Models spot (or gross) delay defects. Line-delay fault – A transition fault tested through the longest delay path. Two faults per line or gate. Tests are dependent on modeled delays of gates. Gate-delay fault – A gate is assumed to have a delay increase of certain amount (called fault size) while all other gates retain some nominal delays. Gate-delay faults only of certain sizes may be detectable. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

At-Speed Test At-speed test means application of test vectors at the rated-clock speed. Two methods of at-speed test. External test: Vectors may test one or more functional critical (longest delay) paths and a large percentage (~100%) of transition faults. High-speed testers are expensive. Built-in self-test (BIST): Hardware-generated random vectors applied to combinational or sequential logic. Only clock is externally supplied. Non-functional paths that are longer than the functional critical path can be activated and cause a good circuit to fail. Some circuits have initialization problem. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Timing Design & Delay Test
Timing simulation: Critical paths are identified by static (vector-less) timing analysis tools like Primetime (Synopsys). Timing or circuit-level simulation using designer-generated functional vectors verifies the design. Layout optimization: Critical path data are used in placement and routing. Delay parameter extraction, timing simulation and layout are repeated for iterative improvement. Testing: Some form of at-speed test is necessary. PDFs for critical paths and all transition faults are tested. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Problems with Delay Test Application in a Scan Environment
Even if good delay test vectors can be generated, scan can only support very limited two vector test patterns launch-on-shift (“skewed load”) launch-on-capture (“broad side”) Many desired delay timing tests may be impossible to apply in a scan environment. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Launch-on-Shift Scan Based Delay Testing
LOGIC Data In Data Out V1 M U X Flip Flop Scan In V2 Scan Enable Clock Clock Edge 1: Launch V2 (scan = 1) Then switch scan = 0 Clock Edge 2: Capture response to V1 → V change in Flip Flop Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Launch-on-Capture Scan Based Delay Testing
LOGIC Data In Data Out V2 = Response[V1] V1 M U X Flip Flop Scan In Clock Edge 1: Apply V1 (scan = 1) Then switch scan = 0 Clock Edge 2: Capture response to V1 in Flip Flop to launch timed transition. This is V2 Clock Edge 3: Capture response to V2 Scan Enable Clock Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Problems with Testing for Timing Fails at Functional Clock Rate
Timing Margin <V1V2> critical path Timing margins to allow for parameter variations, clock skew, variations in test conditions can make “small” defects undetectable. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

minVDD Testing minVDD is found by repeatedly running the test vectors at different VDD voltages and performing a binary search until the failing voltage is identified within desired accuracy Since binary searches on full vector sets can be expensive, methods have been developed to work with reduced test sets. View it as a slide show first. It will highlight important aspects of your presentation, and give you an example of a presentation that lives up to ITC presentation standards and guidelines. Virus checker: When we created this presentation guide it contained no known viruses. This file was checked by McAfee VShield 4.x software before being distributed to authors. You should use a good, up to date virus checker on this file, and any other file you import from an outside source. Make sure your virus checker’s data files are up to date, too. Keep in mind: the version of this file you are reading may be different from the version we checked! Confidentiality: We respect your copyright, and do not distribute your presentation before the conference. However, we cannot promise strict confidentiality of your presentation before the conference, because others have read access to our FTP sites. Do not include confidential information in your presentation. Test Slide: A test slide is included as a “hidden slide” after the end of this presentation. If you want to do a trial projection, ensure that your projector projects the entire slide, and that aspect ratios are correct. We will use the same test slide at the conference for setup of our projection equipment. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Fmax Testing Fmax Testing finds the highest clock rate for which a circuit passes a given (TDF) test set A binary search using repeated applications of the test set is performed to obtain Fmax Again an abnormal Fmax value compared to neighbors indicates a defect that may cause a functional or reliability failure in the field View it as a slide show first. It will highlight important aspects of your presentation, and give you an example of a presentation that lives up to ITC presentation standards and guidelines. Virus checker: When we created this presentation guide it contained no known viruses. This file was checked by McAfee VShield 4.x software before being distributed to authors. You should use a good, up to date virus checker on this file, and any other file you import from an outside source. Make sure your virus checker’s data files are up to date, too. Keep in mind: the version of this file you are reading may be different from the version we checked! Confidentiality: We respect your copyright, and do not distribute your presentation before the conference. However, we cannot promise strict confidentiality of your presentation before the conference, because others have read access to our FTP sites. Do not include confidential information in your presentation. Test Slide: A test slide is included as a “hidden slide” after the end of this presentation. If you want to do a trial projection, ensure that your projector projects the entire slide, and that aspect ratios are correct. We will use the same test slide at the conference for setup of our projection equipment. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Stress Testing ICs also experience significant early life or “infant mortality” failures (0.2-2%) Infant mortality results from latent manufacturing flaws that are undetectable at initial wafer probe testing Important to screen out such failures using accelerated life cycle or stress tests Burn-in tests exercise circuits at elevated voltages and temperatures for a few hours up to a few days in temperature controlled burn-in “ovens” View it as a slide show first. It will highlight important aspects of your presentation, and give you an example of a presentation that lives up to ITC presentation standards and guidelines. Virus checker: When we created this presentation guide it contained no known viruses. This file was checked by McAfee VShield 4.x software before being distributed to authors. You should use a good, up to date virus checker on this file, and any other file you import from an outside source. Make sure your virus checker’s data files are up to date, too. Keep in mind: the version of this file you are reading may be different from the version we checked! Confidentiality: We respect your copyright, and do not distribute your presentation before the conference. However, we cannot promise strict confidentiality of your presentation before the conference, because others have read access to our FTP sites. Do not include confidential information in your presentation. Test Slide: A test slide is included as a “hidden slide” after the end of this presentation. If you want to do a trial projection, ensure that your projector projects the entire slide, and that aspect ratios are correct. We will use the same test slide at the conference for setup of our projection equipment. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Screening for Burn-in Minimization
High end circuits have nanometer feature sizes and operate on low voltages Stress voltages and temperatures must be carefully (individually) controlled to avoid damaging the circuits >> expensive ovens Needed burn-in times are growing because voltage/temperature stress levels can only be marginally increased from the nominal Some defect types do not accelerate in burn-in Statistical outlier screening is now being also used to minimize burn-in View it as a slide show first. It will highlight important aspects of your presentation, and give you an example of a presentation that lives up to ITC presentation standards and guidelines. Virus checker: When we created this presentation guide it contained no known viruses. This file was checked by McAfee VShield 4.x software before being distributed to authors. You should use a good, up to date virus checker on this file, and any other file you import from an outside source. Make sure your virus checker’s data files are up to date, too. Keep in mind: the version of this file you are reading may be different from the version we checked! Confidentiality: We respect your copyright, and do not distribute your presentation before the conference. However, we cannot promise strict confidentiality of your presentation before the conference, because others have read access to our FTP sites. Do not include confidential information in your presentation. Test Slide: A test slide is included as a “hidden slide” after the end of this presentation. If you want to do a trial projection, ensure that your projector projects the entire slide, and that aspect ratios are correct. We will use the same test slide at the conference for setup of our projection equipment. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Summary Path-delay fault (PDF) models distributed delay defects. It verifies the timing performance of a manufactured circuit. Transition fault models spot delay defects and is testable by modified stuck-at fault tests. Variable-clock method can test delay faults but the test time can be long. Critical paths of non-scan sequential circuits can be effectively tested by rated-clock tests. Delay test methods (including BIST) for non-scan sequential circuits using slow ATE require investigation: Suppression of non-functional path activation in BIST. Difficulty of rated-clock PDF test generation. Long sequences of variable-clock tests. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Motivation Early 1990’s – Fabrication Line had 50 to 1000 defects per million (dpm) chips IBM wants to get 3.4 defects per million (dpm) chips (0 defects, 6 σ) Conventional way to reduce defects: Increasing test fault coverage Increasing burn-in coverage Increase Electro-Static Damage awareness New way to reduce defects: IDDQ Testing – also useful for Failure Effect Analysis Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Principle of IDDQ Testing
Measure IDDQ current through Vss bus Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Idealized IDDQ Probability Distribution Function for Good and Bad chips
Current threshold Trade-off between field returns (DPM) and yield loss Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Stuck-at Faults Detected by IDDQ Tests
Bridging faults with stuck-at fault behavior Levi – Bridging of a logic node to VDD or VSS – few of these Transistor gate oxide short of 1 kΩ to 5 kΩ Floating MOSFET gate defects – do not fully turn off transistor Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

NAND Open Circuit Defect – Floating gate

Floating Gate Defects Small break in logic gate inputs (100 – 200 Angstroms) lets wires couple by electron tunneling Delay fault and IDDQ fault Large open results in stuck-at fault – not detectable by IDDQ test If Vtn < Vfn < VDD - | Vtp | then detectable by IDDQ test Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Delay Faults Most random CMOS defects cause a timing delay fault, not catastrophic failure Many delay faults detected by IDDQ test – late switching of logic gates keeps IDDQ elevated Delay faults not detected by IDDQ test Resistive via fault in interconnect Increased transistor threshold voltage fault Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Leakage Faults Gate oxide shorts cause leaks between gate & source or gate & drain Mao and Gulati leakage fault model: Leakage path flags: fGS, fGD, fSD, fBS, fBD, fBG G = gate, S = source, D = drain, B = bulk Assume that short does not change logic values Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Weak Faults nFET passes logic 1 as 5 V – Vtn
pFET passes logic 0 as 0 V + |Vtp| Weak fault – one device in C-switch does not turn on Causes logic value degradation in C-switch Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Instrumentation Problems
Need to measure < 1 μA current at clock > 10 kHz Off-chip IDDQ measurements degraded Pulse width of CMOS IC transient current Impedance loading of tester probe Current leakages in tester High noise of tester load board Much slower rate of current measurement than voltage measurement Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Sematech Study IBM Graphics controller chip – CMOS ASIC, 166,000 standard cells 0.8 mm static CMOS, 0.45 μm Lines (Leff), 40 to 50 MHz Clock, 3 metal layers, 2 clocks Full boundary scan on chip Tests: Scan flush – 25 ns latch-to-latch delay test 99.7 % scan-based stuck-at faults (slow 400 ns rate) 52 % SAF coverage functional tests (manually created) 90 % transition delay fault coverage tests 96 % pseudo-stuck-at fault cov. IDDQ Tests Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Sematech Results Test process: Wafer Test → Package Test →
Burn-In & Retest → Characterize & Failure Analysis Data for devices failing some, but not all, tests. IDDQ (5 μA limit) pass 14 6 52 pass 6 1 36 fail fail 1463 34 13 1251 pass fail 7 1 8 pass fail pass fail Scan-based Stuck-at Scan-based delay Functional Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Sematech Conclusions Hard to find point differentiating good and bad devices for IDDQ & delay tests High # passed functional test, failed all others High # passed all tests, failed IDDQ > 5 μA Large # passed stuck-at and functional tests Failed delay & IDDQ tests Large # failed stuck-at & delay tests Passed IDDQ & functional tests Delay test caught delays in chips at higher Temperature burn-in – chips passed at lower T. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Limitations of IDDQ Testing
Sub-micron technologies have increased leakage currents Transistor sub-threshold conduction Harder to find IDDQ threshold separating good and bad chips IDDQ tests work: When average defect-induced current greater than average good IC current Small variation in IDDQ over test sequence and between chips Now less likely to obtain two conditions Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Current Limit Setting Should try to get it < 1 μA
Histogram for 32 bit microprocessor Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Failure Distribution in Hewlett-Packard Chip

Three processing lots of IDDQ data for a single product.
The Problem with using a single IDDQ threshold Three processing lots of IDDQ data for a single product. Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Stepped threshold IDDQ
Stepped threshold limits lead to unnecessary yield loss at faster end on LOT 1 but do not adequately screen outliers on the slower end especially on LOT 2. Both lots are the same product and were fabricated and tested at the same location Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Neighborhood Selection for IDDQ Outlier Screening at Wafer Sort
Distribution variance: (a) original IDDQ measurements; (b) improved variance resulting from nearest-neighbor estimation (b) Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

% Functional Failures After 100 Hours Life Test
Work of McEuen at Ford Microelectronics Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

IDDQ Built-in Current Testing – Maly and Nigh
Build current sensor into ground bus of device-under-test Voltage drop device and comparator Compares virtual ground VGND with Vref at end of each clock – VGND > Vref only in bad circuits Activates circuit breaker when bad device found Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Summary IDDQ tests improve reliability, find defects causing:
Delay, bridging, weak faults Chips damaged by electro-static discharge No natural breakpoint for current threshold Get continuous distribution – bimodal would be better Conclusion: now need stuck-fault, IDDQ, and delay fault testing combined Still uncertain whether IDDQ tests will remain useful as chip feature sizes shrink further Copyright 2001 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 2)

Memory Test Memory organization Memory test complexity
Faults and fault models MATS+ march test Address Decoder faults Summary References Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Test Time in Seconds (Memory Cycle Time 60ns)
Size Number of Test Algorithm Operations n bits 1 Mb 4 Mb 16 Mb 64 Mb 256 Mb 1 Gb 2 Gb n 0.06 0.25 1.01 4.03 16.11 64.43 128.9 n × log2n 1.26 5.54 24.16 104.7 451.0 1932.8 3994.4 n3/2 64.5 515.4 1.2 hr 9.2 hr 73.3 hr 586.4 hr hr n2 18.3 hr 293.2 hr hr hr hr hr hr Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

SRAM Fault Modeling Examples
SA0 SAF AF+SAF SA0 TF <↓/0> TF <↑/1> SCF <0;0> SCF <1;1> SA0 Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

DRAM Fault Modeling SA1+SCF SA1 AND Bridging Fault (ABF) SA0 ABF ABF

SRAM Only Fault Models Faults found only in SRAM
Open-circuited pull-up device Excessive bit line coupling capacitance Model DRF CF Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

DRAM Only Fault Models Faults only in DRAM Model
Data retention fault (sleeping sickness) Refresh line stuck-at fault Bit-line voltage imbalance fault Coupling between word and bit line Single-ended bit-line voltage shift Precharge and decoder clock overlap Model DRF SAF PSF CF AF Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Reduced Functional Faults
Stuck-at fault Transition fault Coupling fault Neighborhood Pattern Sensitive fault* SAF TF CF NPSF * M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000, Chapter 9. Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Stuck-at Faults Test Condition: For each cell, read a 0 and a 1.
< /0> (< /1>) A A Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Transition Faults Cell fails to make a 0 → 1 or 1 → 0 transition.
Test Condition: Each cell must have an ↑ transition and a ↓ transition, and be read each time before making any further transitions. <↑/0>, <↓/1> <↑/0> transition fault Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Coupling Faults Coupling Fault (CF): Transition in bit j (aggressor) causes unwanted change in bit i (victim) 2-Coupling Fault: Involves 2 cells, special case of k-Coupling Fault Must restrict k cells for practicality Inversion (CFin) and Idempotent (CFid) Coupling Faults -- special cases of 2-Coupling Faults Bridging and State Coupling Faults involve any # of cells Dynamic Coupling Fault (CFdyn) -- Read or write on j forces i to 0 or 1 Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

State Transition Diagram of Two Good Cells, i and j

State Transition Diagram for CFin < ↑ ; ↕ >

State Coupling Faults (SCF)
Aggressor cell or line j is in a given state y and that forces victim cell or line i into state x < 0;0 >, < 0;1 >, < 1;0 >, < 1;1 > Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

March Test Elements M0: { March element (w0) }
for cell := 0 to n - 1 (or any other order) do write 0 to A [cell]; M1: { March element (r0, w1) } for cell := 0 to n - 1 do read A [cell]; { Expected value = 0} write 1 to A [cell]; M2: { March element (r1, w0) } for cell := n – 1 down to 0 do read A [cell]; { Expected value = 1 } Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

{ (w0); (r0, w1, r1); (r1, w0, r0); (r0) }
March Tests Algorithm MATS MATS+ MATS++ MARCH X MARCH C- MARCH A MARCH Y MARCH B Description { (w0); (r0, w1); (r1) } { (w0); (r0, w1); (r1, w0) } { (w0); (r0, w1); (r1, w0, r0) } { (w0); (r0, w1); (r1, w0); (r0) } { (w0); (r0, w1); (r1, w0); (r0, w1); (r1, w0); (r0) } { (w0); (r0, w1, w0, w1); (r1, w0, w1); (r1, w0, w1, w0); (r0, w1, w0) } { (w0); (r0, w1, r1); (r1, w0, r0); (r0) } { (w0); (r0, w1, r1, w0, r0, w1); (r1, w0, w1); (r1, w0, w1, w0); (r0, w1, w0) } Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Address Decoder Faults (ADFs)
Address decoding error assumptions: Decoder does not become sequential Same behavior during both read and write Multiple ADFs must be tested for Decoders can have CMOS stuck-open faults Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Theorem A March test satisfying conditions 1 & 2 detects all address decoder faults. ... Means any # of read or write operations Before condition 1, must have wx element x can be 0 or 1, but must be consistent in test Condition 1 2 March element (rx, …, w x ) (r x , …, wx) Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

March Test Fault Coverage
Algorithm MATS MATS+ MATS++ MARCH X MARCH C- MARCH A MARCH Y MARCH B SAF All ADF Some All TF All CF in All CF id All CF dyn All SCF All Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

March Test Complexity Algorithm Complexity MATS 4n MATS+ 5n MATS++ 6n
MARCH X MARCH C- MARCH A MARCH Y MARCH B Complexity 4n 5n 6n 10n 15n 8n 17n Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

MATS+ Example Cell (2,1) SA0 Fault
MATS+: { M0: (w0); M1: (r0, w1); M2: (r1, w0) } Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

MATS+ Example Cell (2, 1) SA1 Fault
MATS+: { M0: (w0); M1: (r0, w1); M2: (r1, w0) } Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

MATS+ Example Multiple AF: Addressed Cell Not Accessed; Data Written to Wrong Cell
Cell (2,1) is not addressable Address (2,1) maps onto (3,1), and vice versa Cannot write (2,1), read (2,1) gives random data MATS+: { M0: (w0); M1: (r0, w1); M2: (r1), w0 } Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Memory Test Summary Multiple fault models are essential
Combination of tests is essential: March test – SRAM and DRAM Other tests NPSF – DRAM DC parametric – SRAM and DRAM AC parametric – SRAM and DRAM Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Memory NPSF and Parametric Test
Definitions of NPSFs NPSF test algorithms Parametric tests Summary References Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Neighborhood Pattern Sensitive Faults
Definitions: Neighborhood – Immediate cluster of k cells whose operation makes a base cell fail Base cell – A cell under test Deleted neighborhood – A neighborhood without the base cell ANPSF – Active NPSF APNPSF – Active and Passive NPSF PNPSF – Passive NPSF SNPSF -- Static NPSF Assumption: Read operations are fault-free Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Type-1 Active NPSF Active: Base cell changes when any one deleted neighborhood cell has a transition Condition for detection & location: Each base cell must be read in state 0 and state 1, for all possible deleted neighborhood pattern changes. C i,j <d0, d1, d3, d4 ; b> C i,j <0, ↓ , 1, 1; 0> and C i,j <0, ↓ , 1, 1; ↕ > 2 1 3 4 2 – base cell 0, 1, 3 and 4 – deleted neighborhood cells Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Type-2 Active NPSF Used when diagonal couplings are significant, and do not necessarily cause horizontal/vertical coupling 4 – base cell 0, 1, 2, 3, 5, 6, 7 and 8 – deleted neighborhood cells 1 5 4 3 2 6 7 8 Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Passive NPSF Passive: A certain neighborhood pattern prevents the base cell from changing Condition for detection and location: Each base cell must be written and read in state 0 and in state 1, for all deleted neighborhood pattern changes. ↑ / 0 ( ↓ /1) – Base cell fault effect indicating that base cannot change Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Static NPSF Static: Base cell forced into a particular state when deleted neighborhood contains particular pattern. Differs from active – need not have a transition to sensitize SNPSF Condition for detection and location: Apply all 0 and 1 combinations to k-cell neighborhood, and verify that each base cell was written. Ci,j < 0, 1, 0, 1; - / 0> and Ci,j < 0, 1, 0, 1; - / 1> Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

NPSF Fault Detection and Location Algorithm
write base-cells with 0; loop apply a pattern; { it could change the base-cell from 0 to 1. } read base-cell; endloop; write base-cells with 1; apply a pattern; { it could change the base-cell from 1 to 0. } Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Number of Neighborhood Patterns
Active Neighborhood Patterns (ANP) Base cell 0 and 1 ↑ and ↓ transitions in k-1 cells All 0-1 patterns in k-2 cells 2(k-1) 2×2k-2 = (k-1) 2k patterns Passive Neighborhood Patterns (PNP) Base cell ↑ and ↓ transition All 0-1 patterns in k-1 cells 2×2k-1 = 2k patterns Total APNP patterns = (k-1) 2k + 2k = k 2k Static Neighborhood Patterns (SNP) = 2k Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Hamiltonian Path, k = 5 Hamiltonian path for SNPSF Deleted
1110 1111 Hamiltonian path for SNPSF Deleted neighborhood patterns 1010 1011 0110 0111 1100 1101 end 0010 0011 1000 1001 0100 0101 0000 0001 Eulerian path for ANPSF start Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Fault Coverage Hierarchy
APNPSF SNPSF ANPSF PNPSF TF SAF Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Parametric (Electrical) Testing
Test for: Major voltage / current / delay deviation from part data book value Unacceptable operation limits Divided bit-line voltage imbalance in RAM RAM sleeping sickness – broken capacitor, leaks – shortens refresh interval Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

DC Parametric Tests Production test – done during burn-in
Applied to all chips Chips experience high temperature + over-voltage power supply Catches initial, early lifetime component failures – avoid selling chips that fail soon Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Test Output Leakage Current
1. 2. 3. 4. 5. 6. 7. Apply high to chip select, deselect chip Set chip pins to be in tri-state mode Force high on each data-out line – measure IOZ Force low on each data-out line – measure IOZ Select chip (low on chip select) Set read, force high on each address/data line, measure II Set read, force low on each address/data line, Possible Test Outcomes: IOZ < 10 mA and II < 10 mA (passes) IOZ ≥ 10 mA (fails) II ≥ 10 mA (fails) Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Voltage Bump Test Tests if power supply variations make RAM read out bad data – DRAM C shorted to supply 1. 2. 3. 4. Zero out memory. Increase supply above VCC in 0.01 V steps. For each voltage, read memory. Stop as soon as 1 is read anywhere, record voltage as Vhigh Fill memory with 1’s. Decrease supply below VCC in 0.01 V steps. 0 is read anywhere, record voltage as Vlow. Possible Test Outcomes: Vhigh and Vlow inconsistent with data book (fails) Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

AC Parametric Tests Set a DC bias voltage level on pins
Apply AC voltages at some frequencies & measure terminal impedance or dynamic resistance Determines chip delays caused by input & output C’s No information on functional data capabilities or DC parameters Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Access Time Tests Characterization:
1. 2. 3. 4. Split memory into 2 halves. Write 0’s in 1st half and 1’s in other half. Read entire memory and check correctness. Alternate between addresses in two halves Speed up read access time until reading fails, and take that time as access time delay. Characterization: Use MATS++ with increasingly shorter access time until failure. Use March C instead of MATS++. Production test: run MATS++ at specified access time, and see if memory fails. Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Running Time Tests Method: Perform read operations of 0s and 1s from
alternating addresses at specified rapid speed. Alternate characterization method: Alternate read operations at increasingly rapid speeds until an operation fails. Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Sense Amplifier Recovery Fault Tests
Write operation followed by read/write at different address Method: 1 Write repeating pattern dddddddd to memory locations (d is 0 or 1); 2 Read long string of 0s (1s) starting at 1st location up to location with d. 3 Read single 1 (0) from location with d. 4 Repeat Steps 2 and 3, but writing rather than reading in Step 2. Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Memory Test Summary Multiple fault models are essential
Combination of tests is essential: March – SRAM and DRAM NPSF – DRAM DC Parametric – Both AC Parametric – Both Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

References on Memory R. D. Adams, High Performance Memory Testing, Boston: Springer, 2002. M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Boston: Springer, 2000. K. Chakraborty and P. Mazumder, Fault Tolerance and Reliability Techniques for High-Density Random-Access Memories, Upper Saddle River, New Jersey: Prentice Hall PTR, 2002. K. Chakraborty and P. Mazumder, Testing and Testable Design of High-Density Random-Access Memories, Boston: Springer, 1996. B. Prince, High Performance Memories, Revised Edition, Wiley, 1999 A. K. Sharma, Semiconductor Memories: Testing Technology, and Reliability, Piscataway, New Jersey: IEEE Press, 1997. A. J. van de Goor, Testing Semiconductor Memories, Chichester, UK: Wiley Interscience, 1991, reprinted by ComTex, Gouda, The Netherlands ( Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Scan Design for Testability (DFT)

Scan Design Circuit is designed using pre-specified design rules.
Test structure (hardware) is added to the verified design: Add a test control (TC) primary input. Replace flip-flops by scan flip-flops (SFF) and connect to form one or more shift registers in the test mode. Make input/output of each scan shift register controllable/observable from PI/PO. Use combinational ATPG to obtain tests for all testable faults in the combinational logic. Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test. Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Scan Structure PI PO SFF Combinational logic SCANOUT SFF SFF TC or TCK
Not shown: CK or MCK/SCK feed all SFFs. SCANIN Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Scan Design Rules Use only clocked D-type of flip-flops for all state variables. At least one PI pin must be available for test; more pins, if available, can be used. All clocks must be controlled from PIs. Clocks must not feed data inputs of flip-flops. Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Correcting a Rule Violation
All clocks must be controlled from PIs. Comb. logic D1 Q FF Comb. logic D2 CK Comb. logic Q D1 Comb. logic D2 FF CK Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Scan Flip-Flop (SFF) D Master latch Slave latch TC Q MUX Q SD CK
Logic overhead MUX Q SD CK D flip-flop CK Master open Slave open t Normal mode, D selected Scan mode, SD selected TC t Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Level-Sensitive Scan-Design Flip-Flop (LSSD-SFF)
Master latch Slave latch D Q MCK Q SCK D flip-flop SD MCK Normal mode Logic overhead TCK MCK TCK Scan mode TCK SCK t Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Adding Scan Structure PI PO SFF Combinational logic SCANOUT SFF SFF
TC or TCK Not shown: CK or MCK/SCK feed all SFFs. SCANIN Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Comb. Test Vectors I1 I2 O1 O2 PI PO Combinational logic SCANIN TC
SCANOUT S1 S2 N1 N2 Next state Present state Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Combinational Test Vectors
Don’t care or random bits PI SCANIN S1 S2 TC O1 O2 PO SCANOUT N1 N2 Sequence length = (ncomb + 1) nsff + ncomb clock periods ncomb = number of combinational vectors nsff = number of scan flip-flops Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Testing Scan Register Scan register must be tested prior to application of scan test sequences. A shift sequence of length nsff+4 in scan mode (TC = 0) produces 00, 01, 11 and 10 transitions in all flip-flops and observes the result at SCANOUT output. Total scan test length: (ncomb + 2) nsff + ncomb + 4 clock periods. Example: 2,000 scan flip-flops, 500 comb. vectors, total scan test length ~ 106 clocks. Multiple scan registers reduce test length. Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Multiple Scan Registers
Scan flip-flops can be distributed among any number of shift registers, each having a separate scanin and scanout pin. Test sequence length is determined by the longest scan shift register. Just one test control (TC) pin is essential. PI/SCANIN PO/ SCANOUT Combinational logic M U X SFF SFF SFF TC CK Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Scan Overheads IO pins: One pin necessary. Area overhead:
Gate overhead = [4 nsff/(ng+10nff)] x 100%, where ng = comb. gates; nff = flip-flops; Example – ng = 100k gates, nff = 2k flip-flops, overhead = 6.7%. More accurate estimate must consider scan wiring and layout area. Performance overhead: Multiplexer delay added in combinational path; approx. two gate-delays. Flip-flop output loading due to one additional fanout; approx. 5-6%. Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Hierarchical Scan Scan flip-flops are chained within subnetworks before chaining subnetworks. Advantages: Automatic scan insertion in netlist Circuit hierarchy preserved – helps in debugging and design changes Disadvantage: Non-optimum chip layout. Scanin Scanout SFF1 SFF4 SFF1 SFF3 Scanin Scanout SFF2 SFF3 SFF4 SFF2 Hierarchical netlist Flat layout Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Optimum Scan Layout X’ X SFF cell IO pad SCANIN Flip- flop cell Y Y’
TC SCAN OUT Routing channels Active areas: XY and X’Y’ Interconnects Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Scan Area Overhead Linear dimensions of active area: X = (C + S) / r
X’ = (C + S + aS) / r Y’ = Y + ry = Y + Y(1 – b) / T Area overhead X’Y’ – XY = ────── x 100% XY 1 – b = [(1+as)(1+ ────) – 1] x 100% T = (as + ─── ) x 100% y = track dimension, wire width+separation C = total comb. cell width S = total non-scan FF cell width s = fractional FF cell area = S/(C+S) a = SFF cell width fractional increase r = number of cell rows or routing channels b = routing fraction in active area T = cell height in track dimension y Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Example: Scan Layout 2,000-gate CMOS chip
Fractional area under flip-flop cells, s = 0.478 Scan flip-flop (SFF) cell width increase, a = 0.25 Routing area fraction, b = 0.471 Cell height in routing tracks, T = 10 Calculated overhead = 17.24% Actual measured data: Scan implementation Area overhead Normalized clock rate ______________________________________________________________________ None Hierarchical % Optimum layout % Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

ATPG Example: S5378 Original 2,781 179 0.0% 4,603 35/49 70.0% 70.9%
0.0% 4,603 35/49 70.0% 70.9% 5,533 s 414 Full-scan 2,781 179 15.66% 4,603 214/228 99.1% 100.0% 5 s 585 105,662 Number of combinational gates Number of non-scan flip-flops (10 gates each) Number of scan flip-flops (14 gates each) Gate overhead Number of faults PI/PO for ATPG Fault coverage Fault efficiency CPU time on SUN Ultra II, 200MHz processor Number of ATPG vectors Scan sequence length Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Timing and Power Small delays in scan path and clock skew can cause race condition. Large delays in scan path require slower scan clock. Dynamic multiplexers: Skew between TC and TC signals can cause momentary shorting of D and SD inputs. Random signal activity in combinational circuit during scan can cause excessive power dissipation. Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Boundary Scan Test Logic

Instruction Register Loading

System View of Interconnect

Elementary Boundary Scan Cell

Serial Boundary Scan Edge connector
PCB or MCM Edge connector Other implementations: 1. Parallel scan, 2. Multiple scans. Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Summary Scan is the most popular DFT technique: Advantages:
Rule-based design Automated DFT hardware insertion Combinational ATPG Advantages: Design automation High fault coverage; helpful in diagnosis Hierarchical – scan-testable modules are easily combined into large scan-testable systems Moderate area (~10%) and speed (~5%) overheads Disadvantages: Large test data volume and long test time Basically a slow speed (DC) test Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Exercise 5 What is the main advantage of scan method?
Given that the critical path delay of a circuit is 800ps and the scan multiplexer adds a delay of 200ps, determine the performance penalty of scan as percentage reduction in the clock frequency. Assume 20% margin for the clock period and no delay due to the extra fanout of flip-flop outputs. How will you reduce the test time of a scan circuit by a factor of 10? Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Exercise 5 Answers What is the main advantage of scan method?
Only combinational ATPG (with lower complexity) is used. Given that the critical path delay of a circuit is 800ps and the scan multiplexer adds a delay of 200ps, determine the performance penalty of scan as percentage reduction in the clock frequency. Assume 20% margin for the clock period and no delay due to the extra fanout of flip-flop outputs. Clock period of pre-scan circuit = = 960ps Clock period for scan circuit = = 1200ps Clock frequency reduction = 100×( )/1200 = 20% How will you reduce the test time of a scan circuit by a factor of 10? Form 10 scan registers, each having 1/10th the length of a single scan register. Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

BIST Built-In Self-Test

BIST Process Test controller – Hardware that activates self-test simultaneously on all PCBs Each board controller activates parallel chip BIST Diagnosis effective only if very high fault coverage Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

BIST Motivation Useful for field test and diagnosis (less expensive than a local automatic test equipment) Software tests for field test and diagnosis: Low hardware fault coverage Low diagnostic resolution Slow to operate Hardware BIST benefits: Lower system test effort Improved system maintenance and repair Improved component repair Better diagnosis Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

BIST Architecture Note: BIST cannot test wires and transistors:
From PI pins to Input MUX From POs to output pins Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Pattern Generation Store in ROM – too expensive Exhaustive
Pseudo-exhaustive Pseudo-random (LFSR) – Preferred method Binary counters – use more hardware than LFSR Modified counters Test pattern augmentation LFSR combined with a few patterns in ROM Hardware diffracter – generates pattern cluster in neighborhood of pattern stored in ROM Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Random Pattern Testing
Bottom: Random- Pattern Resistant circuit Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Pseudo-Random Pattern Generation
Standard Linear Feedback Shift Register (LFSR) Produces patterns algorithmically – repeatable Has most of desirable random # properties Need not cover all 2n input combinations Long sequences needed for good fault coverage Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Standard n-Stage LFSR Implementation
Autocorrelation – any shifted sequence same as original in 2n-1 – 1 bits, differs in 2n-1 bits If hi = 0, that XOR gate is deleted Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

LFSR Theory Cannot initialize to all 0’s – hangs
If X is initial state, progresses through states X, Ts X, Ts2 X, Ts3 X, … Matrix period: Smallest k such that Tsk = I k LFSR cycle length Described by characteristic polynomial: f (x) = |Ts – I X | = 1 + h1 x + h2 x2 + … + hn-1 xn-1 + xn Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Example External XOR LFSR
Characteristic polynomial f (x) = 1 + x + x3 (read taps from right to left) Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Modular Internal XOR LFSR
Described by companion matrix Tm = Ts T Internal XOR LFSR – XOR gates in between D flip-flops Equivalent to standard External XOR LFSR With a different state assignment Faster – usually does not matter Same amount of hardware X (t + 1) = Tm x X (t) f (x) = | Tm – I X | = 1 + h1 x + h2 x2 + … + hn-1 xn-1 + xn Right shift – equivalent to multiplying by x, and then dividing by characteristic polynomial and storing the remainder Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Example Modular LFSR f (x) = 1 + x2 + x7 + x8
Read LFSR tap coefficients from left to right Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Primitive Polynomials
Want LFSR to generate all possible 2n – 1 patterns (except the all-0 pattern) Conditions for this – must have a primitive polynomial: Monic – coefficient of xn term must be 1 Characteristic polynomial must divide the polynomial 1 – xk for k = 2n – 1, but not for any smaller k value See Appendix B of book for tables of primitive polynomials Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Weighted Pseudo-Random Pattern Generation
F s-a-0 1 256 If p (1) at all PIs is 0.5, pF (1) = 0.58 = Will need enormous # of random patterns to test a stuck-at 0 fault on F – LFSR p (1) = 0.5 We must not use an ordinary LFSR to test this IBM – holds patents on weighted pseudo-random pattern generator in ATE f 1 256 255 256 pF (0) = 1 – = Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Weighted Pseudo-Random Pattern Generator
LFSR p (1) = 0.5 Solution: Add programmable weight selection and complement LFSR bits to get p (1)’s other than 0.5 Need 2-3 weight sets for a typical circuit Weighted pattern generator drastically shortens pattern length for pseudo-random patterns Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Weighted Pattern Gen. w1 w2 1 Inv. p (output) ½ ¼ 3/4 1/8 7/8 1/16
w2 1 Inv. p (output) 3/4 1/8 7/8 1/16 15/16 Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Test Pattern Augmentation
Secondary ROM – to get LFSR to 100% SAF coverage Add a small ROM with missing test patterns Add extra circuit mode to Input MUX – shift to ROM patterns after LFSR done Important to compact extra test patterns Use diffracter: Generates cluster of patterns in neighborhood of stored ROM pattern Transform LFSR patterns into new vector set Put LFSR and transformation hardware in full-scan chain Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Response Compaction Severe amounts of data in CUT response to LFSR patterns – example: Generate 5 million random patterns CUT has 200 outputs Leads to: 5 million x 200 = 1 billion bits response Uneconomical to store and check all of these responses on chip Responses must be compacted Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Definitions Aliasing – Due to information loss, signatures of good and some bad machines match Compaction – Drastically reduce # bits in original circuit response – lose information Compression – Reduce # bits in original circuit response – no information loss – fully invertible (can get back original response) Signature analysis – Compact good machine response into good machine signature. Actual signature generated during testing, and compared with good machine signature Transition Count Response Compaction – Count # transitions from 0 → 1 and 1 → 0 as a signature Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Transition Counting Details
C (R) = Σ (ri ri-1) for all m primary outputs To maximize fault coverage: Make C (R0) – good machine transition count – as large or as small as possible m i = 1 Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

LFSR for Response Compaction
Use cyclic redundancy check code (CRCC) generator (LFSR) for response compacter Treat data bits from circuit POs to be compacted as a decreasing order coefficient polynomial CRCC divides the PO polynomial by its characteristic polynomial Leaves remainder of division in LFSR Must initialize LFSR to seed value (usually 0) before testing After testing – compare signature in LFSR to known good machine signature Critical: Must compute good machine signature Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Example Modular LFSR Response Compacter
LFSR seed value is “00000” Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Modular MISR Example X0 (t + 1) X1 (t + 1) X2 (t + 1) 1 = X0 (t)
1 = X0 (t) X1 (t) X2 (t) d0 (t) d1 (t) d2 (t) + Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Aliasing Theorems Theorem 15.1: Assuming that each circuit PO dij has probability p of being in error, and that all outputs dij are independent, in a k-bit MISR, Pal = 1/(2k), regardless of initial condition of MISR. Not exactly true – true in practice. Theorem 15.2: Assuming that each PO dij has probability pj of being in error, where the pj probabilities are independent, and that all outputs dij are independent, in a k-bit MISR, Pal = 1/(2k), regardless of the initial condition. Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

STUMPS Architecture SR1 … SRn – 25 full-scan chains, each 200 bits
500 chip outputs, need 25 bit MISR (not 5000 bits) Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

STUMPS Test procedure:
Scan in patterns from LFSR into all scan chains (200 clocks) Switch to normal functional mode and clock 1 x with system clock Scan out chains into MISR (200 clocks) where test results are compacted Overlap Steps 1 & 3 Requirements: Every system input is driven by a scan chain Every system output is caught in a scan chain or drives another chip being sampled Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Alternative Test / Scan Systems

Test-per-Clock BIST - Combines test generation/results compression in FFs

CSTP System Test per clock

Examples of CSTP Systems
CSTP BIST for 4 ASICs at Lucent Technologies: Tested everything on 3 of the 4, except for: Input/Output buffers and Input MUX BIST overheads: logic – 20 %, chip area – 13 % Stuck-at fault coverage – 92 % Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Test Point Insertion BIST does not detect all faults:
Test patterns not rich enough to test all faults Modify circuit after synthesis to improve signal controllability Observability addition – Route internal signal to extra FF in MISR or XOR into existing FF in MISR Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

0 and 1 Injection Force b to 0 when TEST & S are 1

Summary Logic BIST system architecture – Advantages:
Higher fault coverage At-speed test Less system test, field test & diagnosis cost Disadvantage: Higher hardware cost Architectures: test / clock, test / scan Needs DFT for initialization, loop-back, and test points, X state elimination Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Definitions Concurrent BIST – Memory test that happens concurrently with normal system operation Transparent testing – Memory test that is non-concurrent, but preserves the original memory contents from before testing began Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

LFSR and Inverse Pattern LFSR
NOR gate forces LFSR into all-0 state Get all 2n patterns Normal LFSR: G (x) = x3 + x + 1 Inverse LFSR: G (x) = x3 + x2 + 1 Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Up / Down LFSR Preferred memory BIST pattern generator
Satisfies March test conditions M U X 1 M U X 1 D Q M U X 1 D Q M U X 1 D Q X0 X1 X2 Up/Down Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Up / Down LFSR Pattern Sequences
Up Counting 000 100 110 111 011 101 010 001 Down Counting Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Mutual Comparator Test 4 or more memory arrays at same time:
Apply same test commands & addresses to all 4 arrays at same time Assess errors when one of the di (responses) disagrees with the others Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Mutual Comparator System
Memory BIST with mutual comparator Benefit: Need not have good machine response stored or generated Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Parallel Memory March C
Add MUX to inputs of write drivers: Selects normal data input or left neighbor sense amplifier output Creates shift register during self-test Generalize any March test to test n-bit words in array rows (x)n means repeat x operations n times Example: March Cn { (w0)n (r0, w0)n; (r0, w1)n (r1, w1)n; (r1, w0)n (r0, w0)n; (r0, w1)n (r1, w1)n; (r1, w0)n (r0, w0)n; (r0, w0)n (r0, w0)n} Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

MATS+ RAM BIST For single-bit word – can generalize to n-bit words
Need Address MUX – switch row decoder from normal input to address stepper (which is the Up/Down LFSR) # states needed: 2 x # March elements + 3 Three extra states: Start Error Correct Chip area overhead: 1 to 2 % – widely used Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

SRAM BIST with MISR Use MISR to compress memory outputs
Control aliasing by repeating test: With different MISR feedback polynomial With RAM test patterns in reverse order March test: { (w Address); (r Address); (w Address); (r Address); (r Address); (w Address); (r Address); (r Address) } Not proven to detect coupling or address decoder faults Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Transparent Testing Basic rule to preserve memory contents:
Complement stored data in memory an even # of times To make any memory test transparent: Assume that cell c contains bit v Add initial memory read of v to algorithm Replace any write x of cell c with write (x v) operation If last write on c returns v, add extra read and write operations to complement cell contents Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Summary BIST is gaining acceptance for testability insertion due to:
Reduced chip area overhead (only 1-3 % chip area for memory BIST) Allows partitioning of testing problem Memory BIST – widely used, < 1 % overhead Random logic BIST, 13 to 20 % area overheads Experimental method has only 6.5 % overhead Used by IBM and Lucent Technologies in selected products Delay fault BIST – experimental stage Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Test Compression BIST has not been widely adopted because it requires significant circuit modification for Test point insertion to improve coverage X-state elimination for deterministic response compression Test Compression methods attempt to achieve a key benefits of BIST – fast test application and low test data volume with deterministic ATPG vectors Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Test Compression Objective
Minimize test application time in scan based environment Minimize test data volume –the amount of test stimulus and response data stored in the tester memory Test compression can reduce test costs 10-50X Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

Test Compression How it works:
Even after compaction, Test vectors contain many don’t cares Less that 5% of the bits are “care” bits The remaining > 95% do not have to be stored in the tester but can be randomly filled by on chip hardware (decoder) Outputs are compressed in MISRs Test time savings are obtained by using a large number short parallel scan chains Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

High Level Diagram of IBM OPMISR Scan Architecture
Output Compression The slide guide is available in the following file: slidesV4.3.ppt: PowerPoint 2000 format. Viewable also with PowerPoint ’97. High Level Diagram of IBM OPMISR Scan Architecture Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3) 05/18/01 V4.3

Illinois Scan Each Scan input feeds many parallel internal scan chains
Thus one bit from the tester can create many bits on-chip for the scan test vector Problem only if a test needs the bits in the same position in two connected parallel chains to be different – rare occurrence ATPG performed assuming this scan structural limitation can limit such conflicts For a few test hard cases, the chains can be serially configured Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

High Level Diagram of an OPMISR + Scans Architecture (2002)
IBM OPMISR+ The slide guide is available in the following file: slidesV4.3.ppt: PowerPoint 2000 format. Viewable also with PowerPoint ’97. High Level Diagram of an OPMISR + Scans Architecture (2002) Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3) 05/18/01 V4.3

Example Implementation of OPMISR+
The slide guide is available in the following file: slidesV4.3.ppt: PowerPoint 2000 format. Viewable also with PowerPoint ’97. Example Implementation of OPMISR+ Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3) 05/18/01 V4.3

Embedded Deterministic Test (Mentor Graphics)

Reduced Test Application Time
Test time saving from many shorter scan chains Potentially >100X in this example Copyright 2005 Agrawal & Bushnell Hyderabad, July 27-29, 2006 (Day 3)

EDT Output Compression

Design for Testability Theory and Practice

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