1. The Stored Program Computer
1945: John von Neumann
Wrote a report on the stored program concept, known as the First Draft of a Report on EDVAC
also Alan Turing… Konrad Zuse… Eckert & Mauchly…
The basic structure proposed in the draft became known as the “von Neumann machine” (or model).
a memory, containing instructions and data
a processing unit, for performing arithmetic and logical operations
a control unit, for interpreting instructions
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2. von Neumann Model Abstraction of von Neumann
stores both program instructions and data
Control Unit: Orchestrator. Implements a state machine, e.g., combination dial lock, vending machine example.
Draw line from CONTROL UNIT to CONTROL UNIT and so on.
What is a finite state machine? Skip ahead a few slides.
implements a next state function
Abstraction of von Neumann
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3. Memory 2k x m array of stored bits Address Contents Basic Operations
unique (k-bit) identifier of location
Contents
m-bit value stored in location
Basic Operations
LOAD
read a value from a memory location
STORE
write a value to a memory location •
0000
0001
0010
0011
0100
0101
0110
1101
1110
1111
What is the value of Write Enable (WE) for a LOAD operation? WE = 0
What is the value of Write Enable (WE) for a STORE operation? WE = 1
Where do the address lines come from? Memory Address Register
Where do the output lines go to? Memory Data Register
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4. Interface to Memory How does processing unit get data to/from memory?
MAR: Memory Address Register
MDR: Memory Data Register
To LOAD a location (A):
Write the address (A) into the MAR.
Send a “read” signal to the memory.
Read the data from MDR.
To STORE a value (X) to a location (A):
Write the data (X) to the MDR.
Send a “write” signal to the memory.
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5. Hardware Level OrganizationPC
MAR IR
MBR
I/O AR
I/O BR
Ex Unit
CPU
I/O Module
buffers
Main Memory
Instruction
Data
n-1
System
Bus
Major components:
- memory
- central processing unit
- registers
- the fetch/execute cycle
(the hardware process)
PC = program counter
IR = instruction register
MAR = memory address register
MBR = memory buffer register
I/O AR = I/O address register
I/O BR = I/O buffer register
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6. Central Processing Unit
Control
- decodes instructions and manages CPU’s internal resources
Registers
- general-purpose registers available to user processes
- special-purpose registers directly managed in fetch/execute cycle
- other registers may be reserved for use of operating system
- very fast and expensive (relative to memory)
- hold all operands and results of arithmetic instructions (on RISC systems)
- save bits in instruction representation
Data path or arithmetic/logic unit (ALU)
- operates on data
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7. Stored Program Concept
Instructions are collections of bits
Programs are stored in memory, to be read or written just like data PC
MAR IR
MBR
I/O AR
I/O BR
Ex Unit
CPU
Main Memory
Instruction
Data
n-1
memory for data, programs,
compilers, editors, etc.
Fetch & Execute Cycle
Instructions are fetched and put into a special register
Bits in the register "control" the subsequent actions
Fetch the “next” instruction and continue
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8. Stored Program Concept
Of course, on most systems several programs will be stored in memory at any given time.
On most contemporary systems instructions of only one of those will be executed at any given instant. PC
MAR IR
MBR
I/O AR
I/O BR
Ex Unit
CPU
Main Memory
PowerPoint pgm
(machine code)
vim
GIS source code
(data)
g++
The operating system will rapidly switch among the eligible processes, producing the illusion that several programs are executing at the same time.
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9. Fetch Next Instruction
Fetch/Execute Cycle
Sometimes called the hardware process… executes continuously.
Fetch Stage
Execute Stage
Fetch Next Instruction
Execute Instruction
START
HALT
Steps:
- fetch an instruction from memory to the instruction register
- increment the program counter register (by the instruction length)
- decode the instruction (in the control unit)
- fetch operands, if any, usually from registers
- perform the operation (in the data path); this may modify the PC register
- store the results, usually to registers
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10. Contents of registers and memory
Finite State Machine
So, where's the FSM?
Next Instruction
Input
Execute Instruction
Input devices
Current State
Output devices
Contents of registers and memory
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11. Control Unit State Diagram
Here's a state machine diagram for the MIPS control logic we'll be studying:
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