1. Lecture 11 Logistics Last lecture Today HW4 due on Wednesday PLDs
ROMs
Multilevel logic
Today
Timing diagrams
Hazards

2. The “WHY” slide Timing diagram Hazards
Real gates have real delays and it is good to learn how to plot the information with respect to time.
Hazards
Different delays can cause some output to get glitches. If these glitches are used in the next level of calculation, it could cause miscalculation. It is good to know when that happens and how to fix it.

3. Timing diagram (aka waveforms)
Shows time-response of circuits
Can use as sideways truth table
Example: F = A +BC

4. Timing diagrams Real gates have real delays Example: A' • A = 0 time
Delays cause transient F=1 F A B C D
time
width of 3 gate delays

5. Example: F=A+BC in 2-level logic
canonical sum-of-products B F1 A
minimized sum-of-products F2
canonical product-of-sums F3
minimized product-of-sums F4

6. Timing diagram for F = A + BC
Time waveforms for F1 – F4 are identical
Except for timing hazards (glitches)

7. Hazards/glitches Hazards/glitches: Undesired output switching
Occurs when different pathways have different delays
Wastes power (wire switching consumes power)
Causes circuit noise
Dangerous if logic makes a decision while output is unstable
Solutions
Design hazard-free circuits
Difficult when logic is multilevel
Wait until signals are stable

8. Types of hazards Static 1-hazard Static 0-hazard Dynamic hazards
Output should stay logic 1
Gate delays cause brief glitch to logic 0
Static 0-hazard
Output should stay logic 0
Gate delays cause brief glitch to logic 1
Dynamic hazards
Output should toggle cleanly
Gate delays cause multiple transitions 1 1 1 1

9. Static hazards
Often occurs when a literal and its complement momentarily assume the same value
Through different paths with different delays
Causes an (ideally) static output to glitch
A multiplexer A A B S F S S' B F S'
static-0 hazard

10. Timing diagram for F = A + BC
Time waveforms for F1 – F4 are identical
Except for timing hazards (glitches)

11. Example: F=A+BC in 2-level logic1 C
canonical sum-of-products B F1 A
minimized sum-of-products F2
canonical product-of-sums F3
minimized product-of-sums F4

12. Timing diagram for F = A + BC
Time waveforms for F1 – F4 are identical
Except for timing hazards (glitches)

13. Example: F=A+BC in 2-level logic1 C 1
canonical sum-of-products B F1 1 A
minimized sum-of-products F2
canonical product-of-sums F3
minimized product-of-sums F4

14. Dynamic hazards Often occurs when a literal assumes multiple values
Through different paths with different delays
Causes an output to toggle multiple times A 3 A F C 2 B B1 1 B2 C B3 F
Dynamic hazards
Dynamic hazard

15. Eliminating static hazards (only in 2 level logic)
Key idea: Glitches happen when a changing input spans separate K-map encirclements
Example: 1101 to 0101 change can cause a static-1 glitch A AB
F = AC' + A'D CD 00 01 11 10 00 1 1 1 1 A C' 01 F 1 1 D A' 11 D 1 C 10 B

16. Eliminating static hazards (con’t)
Solution: Add redundant K-map encirclements
Ensure that all single-bit changes are covered by same block
First eliminate static-1 hazards: Use SOP form
If need to eliminate static-0 hazards, use POS form A
F = AC' + A'D + C'D AB 00 01 11 10 CD 00 A C' 01 D A' F 11 D C C' 10 D B

17. Summary of hazards We can eliminate static hazards in 2-level logic
For single-bit changes
Eliminating static hazards also eliminates dynamic hazards
Hazards are a difficult problem
Multiple-bit changes in 2-level logic are hard
Static hazards in multilevel logic are harder
Dynamic hazards in multilevel logic are harder yet
CAD tools and simulation/testing are indispensable