1. Floating-Gate Devices / Circuits
Prof. Paul Hasler
Georgia Institute of Technology

2. Channel Current Dependence on Gate Voltage
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9 10
-11
-10 -9 -8 -7 -6
Gate voltage (V)
Drain current (A)
k =
Io = fA
In linear scale, we
have a quadratic
dependence
In log-scale, we
have an exponential
dependence
return

3. Basic Scaling Rules for MOSFETs
Early effect increases (Early voltage) decreases with length ---
to keep the same margin from punchthrough as the previous
generation, the doping must increase
doping  1 / L2 (keeps constant field)
To keep sufficiently high k (subthreshold slope),we must
decrease the oxide thickness.
This slope determines the ratio of on-current to off-current.
(as supplies go down, we need a higher slope)
oxide thickness  1 /L

4. Scaling of MOS Parameters
Relationship between Substrate
Doping and Oxide Thickness
- square relationship keeps a constant
coupling into the surface potential by
keeping the gate and depletion
capacitances the same
Relationship between Oxide
Thickness and Gate Length
At this 4nm oxide thickness boundary:
- the drawn gate length is 160nm
- the substrate doping is 1018 cm-3
- a 1V barrier produces a one-sided
depletion width of 40nm

5. Effect of Velocity SaturationVT
A 76 nm MOSFET

6. Maximum Operating Frequencies
fT = frequency where gain
is unity at a given current

7. DIBL in PFETs in 2mm Process1 2 3 4 5 6 7 10 -1 -9 -8 -7 -6
Drain Current (A)
Drain Voltage (V)
Gate Voltage = 0V
L = 1.25 m m
L = 1.50 m m
L = 1.75 m m V d g
Gate voltage
= 0

8. DIBL in PFETs in 2mm Process1
1.5 2
2.5 3
3.5 4
4.5 10
-11
-10 -9 -8 -7 -6 -5 V d g
Drain current (A)
I = I0 e e
Vd / V0
kVg / UT
V0 = 450mV; k = .422
Drain voltage

9. Impact Ionization The mean rate of an impact-ionization
collision is highly energy dependant
Impact Current is proportional
to source current

10. Overview of Floating-Gate Devices
Information Storage
Floating-Gate Transistor
Modifying Floating-Gate
Charge
UV photo-injection
Electron tunneling
Hot-electron injection

11. Floating-Gate Charge Modification
Decrease Floating-Gate charge
by hot-electron injection
Increase Floating-Gate charge
by electron-tunneling

12. Electron Tunneling
Increasing the applied voltage decreases the effective barrier width
The range of tunneling currents span many orders of magnitude.

13. How do we measure these currents?V1
Measurement scheme used
to characterize floating-gate
devices Cf C2 V2 C3
Vout V3
Vref V4
Used in memory cells
--Epots [Harrison, et. al.] C4

14. Scaling Theory for Electron Tunneling
Tunneling Curve (Theory) for 5nm oxides 3
3.5 4
4.5 10
-18
-17
-16
-15
-14
-13
-12
Oxide Voltage
Oxide Current (A)
Itun = Itun0 e
-Eo/Eox
= Itun0 e
- toxEo/Vox
108mV
Itun = 0.2 e
-(125V)/Vox

15. Tunneling in normal FET operation1 2 3 4 5 6 7 8 9 10
-70
-60
-50
-40
-30
-20
-10
Oxide thickness (nm)
Oxide current at equilibrium 10 20 10 15 10 10
1 year
Hold time on 1fF capacitor 10 5
1 hour 10 10 -5 10
-10 1
1.5 2
2.5 3
3.5 4
4.5 5
Oxide thickness (nm)
To store a value (10 years),
minimum oxide = 35nm
Tunneling occurs normally in
MOSFET operation

16. Electron Transport in a Hot-Electron Injecting nFET

17. Electron Transport in a Hot-Electron Injecting nFET

18. Electron Transport in a Hot-Electron Injecting nFET

19. Measurements and Modeling of Hot-Electron Injection

20. pFET Hot-Electron Injection
The injected electrons are generated
by hole impact ionizations.
Vinj = 430mV
Injection current is proportional to
source current, and is an
exponential function of Fdc.

21. Circuit Model of Injection

22. A 0.25mm Floating-Gate MOSFET
UT/k = 35mV, Ith = 10uA (minimum size)
tox = 5nm, NA = 5 x 10 17
Injection pFET: efficiency at 3.3V
Vinj = 90mV at 3.3V
Iinj = (Is/ Iso) e
-DVd/Vinj
0.6
Tunneling:
Vx = 108 mV
0.32
-DVfg/Vx
Iinj = 2.1 x (Is/ Iso) e

23. Summary of Scaling FG Devices
Near future: Very good floating-gate devices, and
“classical” theory holds reasonably well
(down to L = 100nm, ~2006)
Long term: We have many possibilities (at 50nm and below)
- Storage by thicker oxide FETs
- Basic FETs will tunnel / inject in normal operation