1. The 2nd Cache Replacement Championship (CRC-2)
Sunday June 24, 2017 (Afternoon) at the International Symposium on Computer Architecture (ISCA 2017)

2. Welcome The 2nd Cache Replacement Championship (CRC-2)
Last championship (CRC-1)
7 years ago at ISCA 2009
Motivated new ideas and approaches for the replacement policy
Cache size still grows…
AMD Ryzen 7 (16MB LLC), Threadripper (32MB LLC)
Intel Core i9-7900X (13.75MB LLC)
Increasing cache pressure
Multicore and Cloud workloads
Replacement policy critical issue

3. Submissions Cache replacement code with 4-page paper
32KB storage budget for single-core (128KB for multi-core)
7 papers accepted out of 15 submissions (7/15 ≈ 46.6%)
Asia: 4
Europe: 4
North America: 7

4. Acceptance Metrics Paper quality Replacement policy performance
Each paper has 3 reviewers
Online discussion decided acceptance
Novelty, New contribution, Major improvement, and etc.
Replacement policy performance
Performance is measured in Instructions Per Cycle (IPC)
4 different configurations (2 single-core and 2 multi-core)

5. Methodology 4 different configurations
Configuration 1: Single-core w/o prefetchers
Configuration 2: Single-core w/ L1/L2 data prefetchers
Configuration 3: Multi-core w/o prefetchers
Configuration 4: Multi-core w/ L1/L2 data prefetchers
Traces from SPEC CPU 2006 and CloudSuite
1B instruction SimPoint traces from SPEC CPU 2006
100M instruction sampled traces (6 phases) from CloudSuite

6. Simulation Infrastructure
ChampSim
A trace-based simulator for detailed memory subsystem research (and hopefully for future competitions)
Each part in the microarchitecture can be easily modified and evaluated Ex) branch predictor, prefetchers, replacement policy, DRAM scheduling, DRAM cache, etc …
Full source for simulator publicly available
Licensed under the GPL v2
All traces used at
Special thanks to Babak Falsafi, Mark Sutherland and Javier Picorel for much effort in generating CloudSuite Traces!

7. Workshop Program 20 minutes presentation + 5 minutes Q&A
Papers, presentations slides, and code available on the CRC-2 website

8. 1:30pm to 1:45pm Opening Remarks – Paul V. Gratz
1:45pm to 2:10pm “SHiP++: Enhancing Signature-Based Hit Predictor for Improved Cache Performance” V. Young, C. Chou, A. Jaleel, M. Qureshi (Georgia Institute of Technology)
2:10pm to 2:35pm “Less is More: Leveraging Belady's Algorithm with Demand-based Learning” J. Wang, L. Zhang, R. Panda, L. John (University of Texas at Austin)
2:35pm to 3:00pm “Multiperspective Reuse Prediction” D. Jiménez (Texas A&M University)
3:00pm to 3:30pm Intermission
3:30 to 3:55pm “Cache Replacement Policy Based on Expected Hit Count” A. Vakil-Ghahani, S. Mahdizadeh-Shahri, M. Lotfi-Namin, M. Bakhshalipour, P. Lotfi-Kamran, and H. Sarbazi-Azad (Sharif University of Technology and Institute for Research in Fundamental Sciences (IPM))
3:55pm to 4:20pm “Reuse-Aware Management for Last-Level Caches” P. Faldu, B. Grot (University of Edinburgh)
4:20pm to 4:45pm “Hawkeye Cache Replacement: Leveraging Belady’s Algorithm for Improved Cache Replacement” A. Jain, C. Lin (University of Texas at Austin)
4:45pm to 5:10pm “ReD: A Policy Based on Reuse Detection for a Demanding Block Selection in Last-Level Caches”, J. Díaz, P. Ibáñez, T. Monreal, V. Viñals, J. Llabería (University of Zaragoza)
5:10pm to 5:25pm Closing Remarks – Jinchun Kim

9. Thanks Special thanks to Intel Corp for donating the award prizes!
Program Committee
Mike Ferdman
Daniel Jiménez
Moinuddin Qureshi
Eric Rotenberg
Carole-Jean Wu
Akansha Jain
Babak Falsafi
Organizing Committee
Alaa R. Alameldeen
Chris Wilkerson
Seth Pugsley
Aamer Jaleel
Babak Falsafi
Mark Sutherland
Javier Picorel
Special thanks to Intel Corp for donating the award prizes!
Submission / Web
Gino Chacon