1. A MIPS R2000 Implementation
Introductory CMOS VLSI class
Undergraduates: 30 at HMC, 4 at U of Adelaide
Microarchitecture
Five-stage pipeline and hazard/exceptions units
Booth-encoded, radix-4 multiply/divide unit
512 byte I-/D-caches in core, 4 entry write-buffer
Project Partitioning
Clusters
Microarchitecture (RTL)
Chip (datapath, control, memory, COP0)
Systems (compiler, FPGA emulation, PCB)
Library (Std. cells, PLA)
Schematics/layout in Electric
Custom PLA generator

2. Fabrication Verification DRC/NCC/ERC in Electric
Ad-hoc Verilog behavioral
Random test vector generation
IRSIM switch-level simulations
Single-/dual-FPGA emulation
Fabrication
CIF generated by Electric
AMI Mosis 0.5-mm, 4.5 mm
160k transistors
108-pin PGA

3. Testing/Performance Performance 7.25 MHz, limited by caches
Processor
Vax Score (DMIPS)
Clock Speed (MHz)
DMIPS
/MHz
HMC MIPS
(cache
disabled)
0.36
7.25
0.050
1.08
0.150
DECstation 2100 R2000
11.193 12
SGI Personal Iris 4D/20 R2000
9.812
12.5
Performance
7.25 MHz, limited by caches
Power is MHz
More Information
/Engineering/158/07/project